Need help to design pll with desired phase margin

[kooller]

pll design

Hi,
every one.
I'm now designing a pll with reference clock frequency only 6 times to the bandwidth of the pll loop, and in this case the s-domain model is no longer suitable, and z-domain model must be used to model the pll loop. So in this case, I don't know how to design pll system with desired phase margin. That's if I want to design the pll loop with phase margin of 60 degree, how should I get the pll loop parameter from the z-domain model.
Thanks!

 

[LvW]

z domain model of pll

Hi,
every one.
I'm now designing a pll with reference clock frequency only 6 times to the bandwidth of the pll loop, and in this case the s-domain model is no longer suitable, and z-domain model must be used to model the pll loop. .................

.....".must be used" ? Where does this information comes from ?

 

[biff44]

Re: Need help for pll design

https://books.google.com/books?id=c...=onepage&q=control loop transport lag&f=false

 

[LvW]

Re: Need help for pll design

Hi BIF44 !

Is your contribution a response to my question or to KOOLLER´s question ?
I don´t know what to do with it.

 

[kooller]

Re: Need help for pll design

Hi,
every one.
I'm now designing a pll with reference clock frequency only 6 times to the bandwidth of the pll loop, and in this case the s-domain model is no longer suitable, and z-domain model must be used to model the pll loop. .................

.....".must be used" ? Where does this information comes from ?

Because PLL is a discrete system, in the case the fref=6fu, the s-domain model will deviate from the real situation, and I think z-model will be more suitable.

 

[LvW]

Re: Need help for pll design

Because PLL is a discrete system, in the case the fref=6fu, the s-domain model will deviate from the real situation, and I think z-model will be more suitable.

What do you mean with "discrete system" ? Time discrete ? Amplitude discrete ?
Why do you expect deviations from the "real situation" and what is the reason you "think" that a model in the time discrete z-domain is more "suitable" ?
What is reason for your assumptions ?

 

[AdvaRes]

Re: Need help for pll design

Because PLL is a discrete system, in the case the fref=6fu, the s-domain model will deviate from the real situation, and I think z-model will be more suitable.

Hi,
Could you explain why there will be deviation in the case where fref=6fu ?
What do you mean by discrete system ? Are you talking about ADPLL ?

 

[biff44]

Re: Need help for pll design

Hi BIF44 !

Is your contribution a response to my question or to KOOLLER´s question ?
I don´t know what to do with it.

If I were a mind reader, I would guess that the Kooler is saying that because his loop bandwidth is very big, and he has significant transport lag in his divider chain of the PLL, and does not know how to handle that in the S domain. He is instead thinking he has to use a digital sampling approach (Z domain).

I was pointing out that you can take care of transport lag in the S domain by using a phase delay approximation where the tranfer function of the divider N would be =(e^-Ts)/N, where T is the time delay of the divider chain. This will readily give you the effective phase margin degradation of the time delay.

It might only be 10-20 degrees or so of extra open loop phase shift, but it all adds up!

 

[LvW]

Re: Need help for pll design

I was pointing out that you can take care of transport lag in the S domain by using a phase delay approximation where the tranfer function of the divider N would be =(e^-Ts)/N, where T is the time delay of the divider chain. This will readily give you the effective phase margin degradation of the time delay.
It might only be 10-20 degrees or so of extra open loop phase shift, but it all adds up!

Yes, I can follow you. But this has nothing to do with a change from the s-domain to the (time discrete) z-domain, does it ?

LvW

 

[biff44]

Re: Need help for pll design

DSP engineers use the Z domain because it works very nicely for analyzing a discrete time sampled system, since by definition the ADC is sampling at some finite clock rate. Handling time delay is obvious. It is less obvious in the S domain how to handle time delays, but can be done.

But we need to hear from the original poster about exactly what he is thinking.

Time delay is a real control system problem, and gets worse as bandwidth goes up. A good analogy is you are entering a highway in your car, driving say 40 mph. You then decide to program your gps. As you are going slowly, it is easy to look at the road for 1 second, and then look at your gps screen for 5 seconds. But as you start speeding up, 60 mph, things happen faster, and it is harder to only look at the road 1 second for each 6. Now you are at full speed 100 mph, you take your look off the gps screen, and notice that you are no longer travelling down the centerline, but instead some pothole in the road made the car swerve directly toward the guardrail. The time lag on reporting your position was acceptable going 40 mph, but led to an unstable system going 100 mph.

 

[LvW]

Re: Need help for pll design

DSP engineers use the Z domain because it works very nicely for analyzing a discrete time sampled system, since by definition the ADC is sampling at some finite clock rate. Handling time delay is obvious. It is less obvious in the S domain how to handle time delays, but can be done.

But we need to hear from the original poster about exactly what he is thinking.
...................
.

Yes, that sounds reasonable. It´s a pitty that KOOLLER does not answer our questions and nobody knows what he really needs.
BIF44, you have puzzled me a bit since in KOOLLER´s contribution I did not read anything about time delay. (BTW: I am aware of dead time problems in control systems).
Regards
LvW

 

[kooller]

Re: Need help for pll design

Because PLL is a discrete system, in the case the fref=6fu, the s-domain model will deviate from the real situation, and I think z-model will be more suitable.

What do you mean with "discrete system" ? Time discrete ? Amplitude discrete ?
Why do you expect deviations from the "real situation" and what is the reason you "think" that a model in the time discrete z-domain is more "suitable" ?
What is reason for your assumptions ?

I said PLL is a discrete system is because PFD/CP works like the sample system, and in the paper "Charge-Pump Phase-Lock Loops" writen by Gardner, it said that
"A continuous-time approximation is not valid if the loop bandwidth approaches the input frequency. In that case, the discrete-time-or sampled-nature of the loop must be recognized.In particular, sampling introduces stability problems
that do not exist in continuous time networks; the stability limit for the second -order loop is presented." in paragraph 5.

So Gardner derived the stability limit for large loop bandwidth compared to fin.But I don't know how I can design the pll in this situation with suitable pharse margin, such as 60 degree.

And the phase delay attribute by divider will worsen the pharse margin of the loop only when the delay introduced by divider is comparable to the bandwith of pll loop, so what said by biff4 is another situation.

 

[LvW]

Re: Need help for pll design

Hi KOOLLER,

thanks for clarification and for providing the interesting gardner paper.
Now it´s clear what you mean - but I must confess I´ve no experience in the mentioned time discrete interpretation of the loop. Of course, it is true that a time continuous model of a PLL incorporating switching elements can be only an approximation (as each linear PLL model - even with a pure time continuous PD - is only an approximation).
I would recommend to you as a first approach to start with the linear model and find all parameters using conventional rules. And after this, if you detect some stability problems, you can try to follow Gardners approach. That´s all I can say at the moment.
Good luck.

 

[kooller]

Re: Need help for pll design

Hi KOOLLER,

thanks for clarification and for providing the interesting gardner paper.
Now it´s clear what you mean - but I must confess I´ve no experience in the mentioned time discrete interpretation of the loop. Of course, it is true that a time continuous model of a PLL incorporating switching elements can be only an approximation (as each linear PLL model - even with a pure time continuous PD - is only an approximation).
I would recommend to you as a first approach to start with the linear model and find all parameters using conventional rules. And after this, if you detect some stability problems, you can try to follow Gardners approach. That´s all I can say at the moment.
Good luck.

Yes, I'm now using the s-domain model to compute the parameter of the pll, but when I used the designed parameter in z-domain model, the phase margin will be worsen for about 10 degree, and so I had to tune the parameter in hand, which is very troublesome. So I wonder if we can design the loop parameter from z-domain model for the desired phase margin like what we do in s-domain model.

And thanks you for your reply, and also biff44's reply.