#### kooller

##### Junior Member level 3

**pll design**

Hi,

every one.

I'm now designing a pll with reference clock frequency only 6 times to the bandwidth of the pll loop, and in this case the s-domain model is no longer suitable, and z-domain model must be used to model the pll loop. So in this case, I don't know how to design pll system with desired phase margin. That's if I want to design the pll loop with phase margin of 60 degree, how should I get the pll loop parameter from the z-domain model.

Thanks!