hhnn
Junior Member level 2
Hi all,
I am using IBM 0.13um process. When I run the DRC checking for the layout with the "CELL" option, there was no error. However, when I run it with the "CHIP" option, I encountered many more errors.
GRE1eR: FT must be within E1 >=1.2
The errors are around the E1-LY via connections. Has anyone encountered such an error?
Thank all
I am using IBM 0.13um process. When I run the DRC checking for the layout with the "CELL" option, there was no error. However, when I run it with the "CHIP" option, I encountered many more errors.
GRE1eR: FT must be within E1 >=1.2
The errors are around the E1-LY via connections. Has anyone encountered such an error?
Thank all