I am using IBM 0.13um process. When I run the DRC checking for the layout with the "CELL" option, there was no error. However, when I run it with the "CHIP" option, I encountered many more errors.
GRE1eR: FT must be within E1 >=1.2
The errors are around the E1-LY via connections. Has anyone encountered such an error?
which DRC are you using, assura or calibre? does the error exist when you use the other one with "CHIP" design type? contact MOSIS if you are a customer **broken link removed**
I am using Calibre, haven't tried using the other. I notice that this error located within the capacitor's layout so I can't do anything to fix the error.
If the DRC error is actually within capacitor's layout i would suggest that you contact your pdk provider to fix it with an FCR.Correcting foundry's components layout by yourself is not recommended.But before doing anything,take a look at the design manual for an explanation of the error code.Ofcourse for confirmation you can use assura tool because it uses a different rules file than the one calibre does and maybe the error vanishes.
Looks like you are running recommended rules. Are all the other setting same expect this CELL/CHIP setting ? Which one is E1 and which one is FT in layout ?
Generally setting variable to CHIP runs all the rules, besides cell level rules.