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Need help in Verilog hdl universal shift register test bench

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Shakir Ullah

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please help ma regarding the test bench of the following code. I have tried it but it is not working.

Code Verilog - [expand]
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module ShiftRegister8( 
input sl, sr, clk, 
input [7:0] ParIn, 
input [1:0] m, 
output reg [7:0] ParOut); 
 
always @(negedge clk) begin 
case (m) 
0: ParOut <= ParOut; 
1: ParOut <= {sl, ParOut [7:1]}; 
2: ParOut <= {ParOut [6:0], sr}; 
3: ParOut <= ParIn; 
default: ParOut <= 8'bX; 
endcase 
end 
endmodule
 
// Test bench that i have tried but not working 
 
module TB_ShiftRegister8(); 
reg sl, sr, clk; 
reg [7:0] ParIn; 
reg [1:0] m; 
wire [7:0] ParOut; 
initial 
$monitor ("SL: %b , SR: %b , PARIN: %b , M: %b , PAROUT: %b ", sl, sr, ParIn, m, ParOut); 
initial 
begin 
 
#10 sl = 1; ParIn = 8'b1; m = 0; 
#10 sr = 1; ParIn = 8'b1; m = 1; 
#10 sl = 1; ParIn = 8'b1; m = 2; 
#10 sl = 1; sr = 1; ParIn = 8'b1; m = 3; 
#10 $stop; 
end 
ShiftRegister8 M0 (sl, sr, clk, ParIn, m, ParOut); 
endmodule

 
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You dont generate the clock in your testbench
 

Shakir Ullah

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How can i do it i am new in verilog please help
 

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Code Verilog - [expand]
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reg clk;
initial begin
  clk = 0;
  forever #5 clk = ~clk;
end
 
// or ...
reg clk;
initial begin
  clk = 0;
end
always #5 clk = ~clk;

 

Shakir Ullah

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Now i am getting this Output
# SL: x , SR: x , PARIN: xxxxxxxx , M: xx , PAROUT: xxxxxxxx
# SL: 0 , SR: 0 , PARIN: 00000001 , M: 00 , PAROUT: xxxxxxxx
# SL: 1 , SR: 0 , PARIN: 00000001 , M: 01 , PAROUT: 1xxxxxxx
# SL: 0 , SR: 1 , PARIN: 00000001 , M: 10 , PAROUT: xxxxxxx1
# SL: 1 , SR: 1 , PARIN: 00000001 , M: 11 , PAROUT: 00000001
 
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You didn't originally apply any of the inputs based on a clock so your output is going to match whatever you stimulate the design with.

So your output is correct based on your testbench. If you want it to shift more then you'll have to make sure the signals don't change until you've done all the required shifts.

You should probably at least read some tutorial on testbenches. e.g. https://www.asic-world.com/verilog/art_testbench_writing.html
 

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