module lfsr(out,i,clk,data);
output [9:0] out;
output [500:0]data;
input clk;
integer i;
reg [9:0] out=10'b1x11x0x101;
wire linear_feedback1;
wire linear_feedback2;
assign linear_feedback1 =(out[3]^out[2]);
assign linear_feedback2 =(out[5]^out[1]);
always @(posedge clk)
begin
out <= {out[8],out[7],out[6],out[5],linear_feedback1,out[3],out[2],out[1],out[0], out[4]};
end
always @(posedge clk)
begin
for(i=0;i<=500;i=i+1)
begin
data[i]=out;
end
end
end
endmodule