need help in lfsr project

[Sasi Cm]

module lfsr(out,i,clk,data);
output [9:0] out;
output [500:0]data;
input clk;
integer i;
reg [9:0] out=10'b1x11x0x101;
wire linear_feedback1;
wire linear_feedback2;

assign linear_feedback1 =(out[3]^out[2]);
assign linear_feedback2 =(out[5]^out[1]);
always @(posedge clk)
begin
out <= {out[8],out[7],out[6],out[5],linear_feedback1,out[3],out[2],out[1],out[0], out[4]};
end 
always @(posedge clk)
begin
for(i=0;i<=500;i=i+1)
begin
data[i]=out;
end
end
end
endmodule

i need to store the output of the lfsr continuously in a register.
like this.....if the lfsr output is [3:0]m=1011 0111 1110 1101.....
i have to store it continuously in a register like [15:0]n=1011011111101101....
the above coding store the initial value only.

 

[DFT_designer]

Hi,

I have many comments on your code:
1) You are using synchronous process without reset: always @(posedge clk), this is not good you should add a reset input to reset flip-flops. --> always@(posedge clk or negedge rst) for example
2) You are using a for loop which is not good also for synthesis (especially for asic design, not all synthesizer can synthesize it), you can replace it with a synchronous counter --> and I think this is why you are storing only the first value
3) I didn't understand this reg [9:0] out=10'b1x11x0x101; --> this is rather a vhdl like code, you should use assign or put into module
4) why 2 processes always @(posedge clk) ?
Finally to answer your question, you have just to add a signal in the synchronous process and use an if branch to capture the LFSR output when needed

Regards

 

[mrflibble]

From your code, what is this bit supposed to do?

always @(posedge clk) begin
    for(i=0;i<=500;i=i+1) begin
        data[i]=out;
    end
end

I can see what it is going to do, but I doubt it is what you intend...

 

[Sasi Cm]

From your code, what is this bit supposed to do?

always @(posedge clk) begin
    for(i=0;i<=500;i=i+1) begin
        data[i]=out;
    end
end

I can see what it is going to do, but I doubt it is what you intend...

Here i try to store it continuously in a register here. But it not works.

 

[mrflibble]

But it not works.

Indeed. May I suggest you grab your favorite verilog book and read what a for loop does? Because I suspect it doesn't do what you think.

 

[Sasi Cm]

sure.And i want your suggestion , about how to do that.which condition can i use instead of for loop.

 

[mrflibble]

Actually I was thinking that THAT is what the book is for. But I'll bite for 40%... Can you write a decent functional specification for what you need? That way we don't have to guess or make assumptions regarding your intended requirements. And yes, I have read all the above, so the implication is that what you have written so far is not a clear spec. If you think that is a silly question ... writing clear specifications is a large part of this kind of work.

If you have a decent spec we can give some suggestions.

 

[Sasi Cm]

here i attached my output and my need...

 

[mrflibble]

A document with copy/paste of stuff you already wrote. Interesting...

 

[Sasi Cm]

sorry...i cant understand what you are saying...
is that possible to do this....?

 

[mrflibble]

The .doc attachment is a repetition of old things. If that's all you can provide I'm afraid I can't help, but maybe someone else has some extra free time to flush into communication. Good luck.