What part of implementing this in Verilog is the problem (be very specific, if you expect any help)?
FYI, edaboard members are not FREE consultants, so don't expect someone to write code for you.
If the problem is you don't know Verilog...
a) learn Verilog
b) hire someone that knows Verilog to code this for you (there is a jobs section if you decide to do that).
c) have a friend that "owes you one" that either knows Verilog, can do a, or has money to give you for b.