Hi Bin,
I've recently done a TSMC gate level simulation.
Normally the gate library will be in the form of a big verilog file (or several files), and you need to edit your compile script to include this.
If you're using ModelSim, you need to invoke vsim with the -L option to point it at the technology library.
If your testbench is not written in Verilog, you'll need a mixed Verilog/VHDL/SystemC/whatever license.
If you haven't done a gate level simulation before, be prepared for all sorts of problems. If your design is large it will quickly consume huge amounts of RAM. You may find there are issues with your simulation filling with X values - if that's the case, look to your RAM models and any undriven inputs, which are prime candidates for X propagation.
Good luck!
Siskin