need help for verilog code

[EDA_hg81]

My codes is for realizing the following:

Data_out = (Data_IN>>1 + Data_IN>>2) + Data_IN2;

The first code:

input Data_IN;
input Data_IN2;
output Data_OUT;

reg REG;
reg Data_REG;

assign Data_OUT = Data_REG[8] ? 8'hff : Data_REG[7:0];

always @ ( posedge Clock )
begin
if ( 1 ) begin
Data_REG <= Data_IN >>1;
REG <= Data_REG >>1;
end
if ( 1 )
Data_REG <= Data_IN2 + Data_REG + REG;
end
endmodule

My question is as following:

when Data_IN and Data_IN2 are inputted into the process, the Data_out only can be updated with right data one clock after or Data_out never can get right data?


if I use the second code as following:

input Data_IN;
input Data_IN2;
output Data_OUT;

reg REG;
reg Data_REG;

assign Data_OUT = Data_REG[8] ? 8'hff : Data_REG[7:0];

always @ ( Data_IN,Data_IN2 )
begin
if ( 1 ) begin
Data_REG <= Data_IN >>1;
REG <= Data_REG >>1;
end
if ( 1 )
Data_REG <= Data_IN2 + Data_REG + REG;
end
endmodule

The Data_OUT can be updated right away with right data?


Since this program have Hold timing errors when Data_OUT output to the following module, it is possible for me to put delay in first code?

But I am sure I can use another register to produce delay in the second code.

How do you think which code is faster?

How to put timing constrian in second code if I am using spartan 2E?

Thank you.

 

[tkbits]

In your first code, Data_OUT is immediately updated whenever Data_REG is updated. Data_REG gets updated on the positive edge of Clock.

In the second code, you have a combinatorial (unclocked) block with a signal (variable) on both sides of the same assignment. If you attempt to synthesize this, it can lead to infinite updating, as there is nothing to stop re-evaluation. (Synthesis does not use sensitivity lists. It checks them only for correctness of simulation model.)

By the way, if (1) is redundant, and does not add any information.

Also, you use <= instead of =. Because of that, the values used on the right hand side are the values existing at the beginning of the block, not the ones acquired through "sequencing".

 

[dsocer]

always @ ( posedge Clock )
begin

Data_REG = Data_IN >>1;
REG = Data_REG >>1;
Data_REG = Data_IN2 + Data_REG + REG;
end

 

[JaneZhong]

<= and = are different.