meghna
Junior Member level 3
Hi,
I am desiging a sigma-delta modulator in 0.35um technology having 5-bit coarse quantization. For the switch capacitor integrator, I have chosen 32 sampling capacitor (Cs) of value 0.3pF each. And the value of integrating capacitor (Ci) is 32*0.3=9.6pf.
Please suggest me some good layout technique for capacitor of this much large value (10pf), where maching is important between Ci and Cs and & Ci+ and Ci-
I think poly1-poly2 cap is the best choice. Should I use just 2 square planes of poly1-poly2 or other techniques can be used.
Thanks and Regards
~Meghna
I am desiging a sigma-delta modulator in 0.35um technology having 5-bit coarse quantization. For the switch capacitor integrator, I have chosen 32 sampling capacitor (Cs) of value 0.3pF each. And the value of integrating capacitor (Ci) is 32*0.3=9.6pf.
Please suggest me some good layout technique for capacitor of this much large value (10pf), where maching is important between Ci and Cs and & Ci+ and Ci-
I think poly1-poly2 cap is the best choice. Should I use just 2 square planes of poly1-poly2 or other techniques can be used.
Thanks and Regards
~Meghna