Hi,
I am desiging a sigma-delta modulator in 0.35um technology having 5-bit coarse quantization. For the switch capacitor integrator, I have chosen 32 sampling capacitor (Cs) of value 0.3pF each. And the value of integrating capacitor (Ci) is 32*0.3=9.6pf.
Please suggest me some good layout technique for capacitor of this much large value (10pf), where maching is important between Ci and Cs and & Ci+ and Ci-
I think poly1-poly2 cap is the best choice. Should I use just 2 square planes of poly1-poly2 or other techniques can be used.
why not reduce ur total capacitance ?
why did u choose 9.6pF for ur integrator ? for noise issue, or matching issue?
by the way, what do u mean "5-bit coarse quantization", I have not heard about that term from books, is it a new technique ?
Hi,
Thanks for your replies. By coarse quantization, I meant internal quantization i.e. 5-bit flash ADC (that needs 32 comparators) and 5-bit DAC (that needs 32 sampling capacitors with switches).
I have chosen 0.3pF for each sampling capacitor, so total value of sampling cap is 32*0.3pF=9.6pF. And that should be the value of integrating capacitor also for a gain of 1 (Cs /Ci).
yeah...PIP capacitor will be the best. But somehow I am not getting a good idea about how to place it.
Yeah..sometimes paracitic capacitance reaches in some 0.xpf. But then what can be the minimun capacitor value, I can safely choose in 0.35um Technology.
(please keep in mind that I will have to multiply this value by 32, and that multiplied value will be the load capacitance for the OTA, so I am avoiding to use large values)