need help about LVDS design

[engronger]

I am designing a lvds transmitter following Andrea Boni 's paper <LVDS I/O interface for Gb/s-per-Pin Operation in 0.35-um CMOS >. and have some problem can not understand , need somebody give a great help .thanks very much
the paper and image i must use see follow . my problem is about Fig 2.
1: what is the limit to Rc and Cc? hwo to give their value?

2: the author make Ra and Rb=100k, how to realize so large a resistor?

3: i find the Vcm 's value become larger and larger , the input i give is a pulse that data stream 2Gbps . i can not understand it ?

4: for better signal integrity, we are connect a cap between Mu , ML's D and S .then i have a question ,are the caps have some limit ?

5: we all know the Rout must match the line 's impedance. then what is it mean? for a 50ohm 's line inpedance, is that to say, M1~M4 the Ron=50ohm,if it is right ,then why there is a Rt-t?


thanks very much
newsun



Added after 5 minutes:

when i want to give the paper ,it alway says "
Sorry but this file has already been posted! Better copy and paste following link into your post, where the same file is located:


"

I am designing a lvds transmitter following Andrea Boni 's paper <LVDS I/O interface for Gb/s-per-Pin Operation in 0.35-um CMOS >. and have some problem can not understand , need somebody give a great help .thanks very much
the paper and image i must use see follow . my problem is about Fig 2.
1: what is the limit to Rc and Cc? hwo to give their value?

2: the author make Ra and Rb=100k, how to realize so large a resistor?

3: i find the Vcm 's value become larger and larger , the input i give is a pulse that data stream 2Gbps . i can not understand it ?

4: for better signal integrity, we are connect a cap between Mu , ML's D and S .then i have a question ,are the caps have some limit ?

5: we all know the Rout must match the line 's impedance. then what is it mean? for a 50ohm 's line inpedance, is that to say, M1~M4 the Ron=50ohm,if it is right ,then why there is a Rt-t?


thanks very much
newsun

 

[chang830]

Let's try to answer part of the items.

1: what is the limit to Rc and Cc? how to give their value?
The Rc-Cc is for the stability of common mode feedback, you need to do the stability analysis(loop analysis) to optimize the value of Rc-Cc.

2: the author make Ra and Rb=100k, how to realize so large a resistor?
I guess you process will provide some high sheet resistance Res, you can use it, it will not consume large area.

3: i find the Vcm 's value become larger and larger , the input i give is a pulse that data stream 2Gbps . i can not understand it ?
That means your common mode feedback loop is not stable, you can vary the Rc and Cc for better stability

4: for better signal integrity, we are connect a cap between Mu , ML's D and S .then i have a question ,are the caps have some limit ?
they of course have some limit. If it is too large, it will affect the setting time.

5: we all know the Rout must match the line 's impedance. then what is it mean? for a 50ohm 's line inpedance, is that to say, M1~M4 the Ron=50ohm,if it is right ,then why there is a Rt-t?
The Rout match the line's impedence, the signal will have good integrity.You can not easily control the Ron of M1~M4 equal 50Ohm, the best way is to terminated it with passsive resistor,I guess.

 

[ravi dixit]

Hi Newsun, according to me 4 ur LVDS design initially u don’t need 2 strictly refer this paper, first try to design a simple LVDS with proper specifications (follow ansi standards strictly (specially common mode & differential range should lie within range specified in standards), also transistors size of LVDS is very very large hence current mirror multiplication ratio will be high, proper modeling of transmission channel, esd protection & bonding pads is needed during simulation, After achieving all this extend ur design 4 current mirrors feedback loop. & at last for driving these large switching transistors of LVDS don't forget to put inverter chain (by considering proper fanout in ur technology)

 

[orbb]

5: we all know the Rout must match the line 's impedance. then what is it mean? for a 50ohm 's line inpedance, is that to say, M1~M4 the Ron=50ohm,if it is right ,then why there is a Rt-t?

The Ron of of M1~M4 is large in this case. The impedance looking into M3, M4 source is no longer 1/gm because of the large drain resistance. Therefore the smallest resistance (that determines the node's impedance) at the output nodes is RT-T =100 Ohms. SInce the architecture is fully differential, you can split RT-T into two resistors to ground, each 50 Ohms.

 

[engronger]

first ,thank all of your help , especially chang830 ,you are so kindhearted to answer all the quesetions here .thanks very much

this is the link to the paper i used on edaboard

Dear chang830 , you answer give me many helps ,but i still have something cannot understand .could you give me more explain?
Let's try to answer part of the items.

1: what is the limit to Rc and Cc? how to give their value?
The Rc-Cc is for the stability of common mode feedback, you need to do the stability analysis(loop analysis) to optimize the value of Rc-Cc.
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
as you know ,the signal input is digital signal , it should be a large singal analysis. then how to do the stability analysis?(i am using cadence spectre)

3: i find the Vcm 's value become larger and larger , the input i give is a pulse that data stream 2Gbps . i can not understand it ?
That means your common mode feedback loop is not stable, you can vary the Rc and Cc for better stability
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~`
thank you ,when i increase the R used to extract the common voltage(RA and RB), it is better.(but i still do not understand why , )

4: for better signal integrity, we are connect a cap between Mu , ML's D and S .then i have a question ,are the caps have some limit ?
they of course have some limit. If it is too large, it will affect the setting time.
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
en ,how can i know the setting time? how to simulate it?

5: we all know the Rout must match the line 's impedance. then what is it mean? for a 50ohm 's line inpedance, is that to say, M1~M4 the Ron=50ohm,if it is right ,then why there is a Rt-t?
The Rout match the line's impedence, the signal will have good integrity.You can not easily control the Ron of M1~M4 equal 50Ohm, the best way is to terminated it with passsive resistor,I guess.
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
the problem is that ,Ron of M1~M4 is not a large one,since it work at triode range , and because of a so large W/L ,the impedance would just be some hundred ohm. if it parallel connect a 100 ohm resistor , in my opinion ,the Rout would be small than 50Ohm. there still do not have a good match.

Added after 4 minutes:

to anilkoul:
the link i give in my topic is the way to the paper on edaboard .
because there alread has one ,i can not upload again


best regards
and maybe we can have a better discussion

newsun

Added after 8 minutes:

thank you for you advice,ravi dixit

now i have finish the architecture, (just follow some paper , and do not have a good understand about ,so there are so many problem )

the largest problem fo my transmitter is the line model ,my line model is gived by a friend,(he use it not for LVDS), i alway feel it is not fitted my system.

best regards

newsun

Added after 7 minutes:

dear orbb
you said
"The Ron of of M1~M4 is large in this case. The impedance looking into M3, M4 source is no longer 1/gm because of the large drain resistanceThe Ron of of M1~M4 is large in this case. The impedance looking into M3, M4 source is no longer 1/gm because of the large drain resistance“
~~~~~~~~~~~~~~~~~~~~~~~
i can not agree with you Maybe
since M1~M4 work in triod range ,1/gds is not still so large ,so the impedance looking into M3,M4 is no longer 1/gm, but a 1/gm parallel with 1/gds ,that is to say ,the impedance change to smaller. and becasue the very larege w/L,the r0 is rather small. are you agree?

best regards
newsun

 

[chang830]

Hi,
Pls. see my comments.

as you know ,the signal input is digital signal , it should be a large singal analysis. then how to do the stability analysis?(i am using cadence spectre)

Yes, the input signal is large signal. But the AC loop analysis also gives you the information about the loop stability. I mean, it do works in large signal condition, but ot is OK for you to do small signal analysis to check the stability.

en ,how can i know the setting time? how to simulate it?

The node would be heavily modulated if the cap is small. It is easy to adjust it with monotoring the transient waveform.

the problem is that ,Ron of M1~M4 is not a large one,since it work at triode range , and because of a so large W/L ,the impedance would just be some hundred ohm. if it parallel connect a 100 ohm resistor , in my opinion ,the Rout would be small than 50Ohm. there still do not have a good match.

You can do the simulation to investiagate the output impedence to check if it is hundred ohm. My point is it is not a good idea with MOS transistor as impedence match because it varies much versus PVT.

Thanks