I can't quite understand your second message, sorry.
I don't know VHDL very well, but maybe this Verilog example will help you. It inputs a 50 MHz clock, doubles it to 100 MHz, and then clocks a simple counter. It synthesizes into a Spartan-3, a Virtex-5, and maybe other FPGA types too.
Code:
module top (clk50, count);
input clk50; // synthesis attribute period clk "50 MHz";
wire clk50dcm, clk100dcm, clk100;
output reg [7:0] count = 0;
DCM dcm100 (.CLKIN(clk50), .RST(1'b0), .CLKFB(clk50dcm), .CLK0(clk50dcm), .CLK2X(clk100dcm));
defparam dcm100.CLKIN_PERIOD = 20.0;
BUFG buf100 (.I(clk100dcm), .O(clk100));
always @ (posedge clk100) begin
count <= count + 1;
end
endmodule
That's only an example. The DCM is highly configurable, so be sure to read the user guide and data sheet for your FPGA, and use whichever DCM connections and parameters are appropriate for your project. Some folks prefer to use the wizard instead because it hides many of those details.