dcm vhdl
this is the code generated from Core generator ..for vertex 4 family for which the freuency range is 32 to 150 Mhz i have given minimum freq 32 Mhz.
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity DCM_Clkx2 is
port ( CLKIN_IN : in std_logic;
RST_IN : in std_logic;
CLKIN_IBUFG_OUT : out std_logic;
CLK0_OUT : out std_logic;
LOCKED_OUT : out std_logic);
end DCM_Clkx2;
architecture BEHAVIORAL of DCM_Clkx2 is
signal CLKIN_IBUFG : std_logic;
signal CLK0_BUF : std_logic;
signal GND_BIT : std_logic;
signal GND_BUS_7 : std_logic_vector (6 downto 0);
signal GND_BUS_16 : std_logic_vector (15 downto 0);
begin
GND_BIT <= '0';
GND_BUS_7(6 downto 0) <= "0000000";
GND_BUS_16(15 downto 0) <= "0000000000000000";
CLKIN_IBUFG_OUT <= CLKIN_IBUFG;
CLKIN_IBUFG_INST : IBUFG
port map (I=>CLKIN_IN,
O=>CLKIN_IBUFG);
CLK0_BUFG_INST : BUFG
port map (I=>CLK0_BUF,
O=>CLK0_OUT);
DCM_ADV_INST : DCM_ADV
generic map( CLK_FEEDBACK => "NONE",
CLKDV_DIVIDE => 2.0,
CLKFX_DIVIDE => 1,
CLKFX_MULTIPLY => 4,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 31.250,
CLKOUT_PHASE_SHIFT => "NONE",
DCM_AUTOCALIBRATION => TRUE,
DCM_PERFORMANCE_MODE => "MAX_SPEED",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => TRUE,
FACTORY_JF => x"F0F0",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map (CLKFB=>GND_BIT,
CLKIN=>CLKIN_IBUFG,
DADDR(6 downto 0)=>GND_BUS_7(6 downto 0),
DCLK=>GND_BIT,
DEN=>GND_BIT,
DI(15 downto 0)=>GND_BUS_16(15 downto 0),
DWE=>GND_BIT,
PSCLK=>GND_BIT,
PSEN=>GND_BIT,
PSINCDEC=>GND_BIT,
RST=>RST_IN,
CLKDV=>open,
CLKFX=>open,
CLKFX180=>open,
CLK0=>CLK0_BUF,
CLK2X=>open,
CLK2X180=>open,
CLK90=>open,
CLK180=>open,
CLK270=>open,
DO=>open,
DRDY=>open,
LOCKED=>LOCKED_OUT,
PSDONE=>open);
end BEHAVIORAL;
I have not tested the code but I have generated the for my work where the I need multiplied bty 6 clk...