// Pin locations for Xilinx Spartan-3E Starter Kit
module top (clk50MHz, clk320MHz, locked2);
(* LOC="C9", PERIOD="50 MHz" *) input clk50MHz;
reg [3:0] count = 0;
wire clk5MHz = count[3];
wire clka, clkb, clkc, locked1;
reg [4:0] reset=0;
(* LOC="A10",SLEW="FAST" *) output clk320MHz;
(* LOC="A6", SLEW="FAST" *) output locked2;
always @ (posedge clk50MHz)
count <= count == 4 ? -5 : count + 1; // divide 50 MHz to 5 MHz
// synthesize 40 MHz from 5 MHz
DCM dcm1 (.CLKIN(clk5MHz), .RST(1'b0), .CLKFB(), .CLK0(), .CLKDV(), .CLKFX(clka), .LOCKED(locked1));
defparam dcm1.CLK_FEEDBACK = "NONE";
defparam dcm1.CLKFX_MULTIPLY = 8;
defparam dcm1.CLKFX_DIVIDE = 1;
defparam dcm1.CLKIN_PERIOD = 200;
BUFG buf1 (.I(clka), .O(clkb));
always @ (posedge clkb)
reset <= {reset,locked1};
// synthesize 320 MHz from 40 MHz
DCM dcm2 (.CLKIN(clkb), .RST(~reset[4]), .CLKFB(), .CLK0(), .CLKDV(), .CLKFX(clkc), .LOCKED(locked2));
defparam dcm2.CLK_FEEDBACK = "NONE";
defparam dcm2.CLKFX_MULTIPLY = 8;
defparam dcm2.CLKFX_DIVIDE = 1;
defparam dcm2.CLKIN_PERIOD = 25;
BUFG buf2 (.I(clkc), .O(clk320MHz));
endmodule
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