module clock2x (clk50, count, locked);
input clk50; // synthesis attribute period clk "50 MHz";
wire clk100;
output reg [7:0] count = 0;
output locked;
dcm2x dcm100 (.CLKIN_IN(clk50), .RST_IN(1'b0), .CLKIN_IBUFG_OUT(), .CLK0_OUT(), .CLK2X_OUT(clk100),.LOCKED_OUT(locked));
always @ (posedge clk100)
begin
count <= count + 1;
end
endmodule
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