I need to design a sampling clock generator for 16 bit ADC (probably LTC2209) that will sample IF in software radio. I dont want to go in details about the architecture but the ADC will not sample at a constant rate ("multistandard" receiver). Sometimes it will be GSM, sometimes just HF panorama. The concept is that the sample rate must be variable as it apparently simplifies the job of software eng. (I know little about it). I have a good GPS stabilized 10MHz and 20MHz reference. One of the methods I know to generate stable , low jitter clock is to use Nth harmonic of the reference. However this way I can get only some common frequencies , but how to get i.e. 101.23MHz (dont ask me why I need this freq, this is just an example, I received a 2 pages long list of frequencies that I have to be able to set precisely). And as I said before this can be done by soldering some components as it is on per PCB basis, but the PCB has to be universal. I figured out that doing it the way described in AN800 above is fine, however I am afraid that phase nose is still too big for a 16b ADC undersampling 300MHz IF.
One of the things I want to know is how do you generate a very low phase noise , precise frequency clock if you don't have a crystal oscillator at this frequency and the frequency is not a multiple of somithing common like 10MHz?
Good 16b performance is needed.