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#### maniana

##### Member level 4
Hi, I need to design a tunable (ideally 1MHz to 200MHz) sampling clock generator for 16bit 130MSPS ADC.
Super low jitter is desirable, 1fs ( I know 1fs is not realistic, although it would be nice to have, as operation in undersampling may be required)
I want to be able to change the frequency of the clock without changing the PCB, so I thought of a structure similar to described in:
pdfserv.maxim-ic.com/en/an/AN800.pdf

I have a GPS stabilized 10MHz and 20MHz TCXO that can provide a reference freq for i.e. the above system.

Could anyone advise on a structure, maybe similar to one described in AN800 above, or any other circuit that can generate a tunable clock for ADC with the lowest possible jitter?

#### tony_lth

I think for fs jitter, you need use OCXO.

#### maniana

##### Member level 4
I have a GPS stabilized reference, stability 10e-11, ppm is not an issue here.
Let me rephrase the question:
How to generate a sample clock suitable for 160MSPS 16bit ADC undersampling 300MHz IF at 134.51MSPS (this is just an example to make sure you can't find a OCXO with f=134.51MHz) if you don't have OCXO, XO etc.. with exactly the frequency of interest ?
You only have a good 10MHz or 20MHz reference frequency.

This is just onee of the problems here.

#### biff44

by "system engineering" I mean to go over the system specifications carefully and figure out why you need such tight specifications. For instance, you can have a DDS based synthesizer which will give you the 1 khz step size you wish for. But there will be much more than 1 fs of jitter. But since most of this jitter will be +/-, statistiaclly it will "average-out" over your ADC sample size and become less important. So you need to ask your DSP processing guy exactly why he is telling you a specification that is 1000 tighter than you can easily achieve. It sounds like the DSP guy does not know what he is doing.

Also keep in mind that if he is parallel processing multiple channels, if you are feeding each channel with the same clock jitter, it will correlate out to a much lower effective jitter (assuming the distribution time delays are ~ matched)

tony_lth

### tony_lth

points: 2

#### rfmw

1 fs ( which is crazy by the way) and \$50 budget? I don't think this goes hand in hand mister. I've been working with LTC 2209 with a clock jitter of around 200-300fs (100Hz-10MHz) and I get 12.5 bits which is already on the limit of the ADC. I'd advise you ultra-low phase-noise XCO + DDS, but you'll end up with several hundreds fs of jitter.

#### maniana

##### Member level 4
I don't expect 1fs, I know this is not realistic, even with unlimited budget. If I can get 150fs I will be happy.
Some time ago I saw TI's presentation where they used one of their DAC to generate a clock. It apparently was better than any DDS and certainly a PLL.
Can anyone of you put a number on how much a DDS (which one ? AD9854?) is better than AD9522 or the circuit from AN800 ?

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#### rfmw

I see that AN800 does not provide the final phase noise performance plot of the PLLed VCO. Would be interesting to see it. The AD9852 and AD9854 have good phase noise performance, comparable to the AD9522 (I keep in mind the Figure 33 in AD9522-4 datasheet). So one should make a careful design review, which solution would give better final phase noise at your requirements. Maybe a DDS used as a reference to the PLLed VCO would give you a good phase noise and small frequency step?

#### tony_lth

One latest article said AD product can reach 200fs, I think that's your object. And the article don't give more details about it.

#### ledum

##### Junior Member level 3
20MHz ref., may be, is too low. Compare, pls. It's my real clock project for AD9230 with AD9517-0 as clock source.

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tony_lth

points: 2