need advice on low jitter clk generator for 16bit ADC

[maniana]

Hi, I need to design a tunable (ideally 1MHz to 200MHz) sampling clock generator for 16bit 130MSPS ADC.
Super low jitter is desirable, 1fs ( I know 1fs is not realistic, although it would be nice to have, as operation in undersampling may be required)
I want to be able to change the frequency of the clock without changing the PCB, so I thought of a structure similar to described in:
pdfserv.maxim-ic.com/en/an/AN800.pdf

I have a GPS stabilized 10MHz and 20MHz TCXO that can provide a reference freq for i.e. the above system.

Could anyone advise on a structure, maybe similar to one described in AN800 above, or any other circuit that can generate a tunable clock for ADC with the lowest possible jitter?

A common sense is required when thinking about the price. I would put a soft limit at around 50$ for critical components.

 

[biff44]

When you say "tuning", what exactly do you mean. How about a 1 MHz step size, for instance?

 

[maniana]

The tuning does not have to be "live". It can be done by soldering some resistors, replacing a crystal oscillator etc... but I will also need some control in software as I want a 1kHz resolution or better. But again this is something that is done once for a PCB.
I will need some non typical frequecies hence the step 1kHz, the lower the step the better but it is not a critical spec.

 

[biff44]

I think you might want to do some system engineering before you proceed. There is quantization noise and thermal noise floor noise issues to worry about too. But if you ignore those, a typical good frequency synthesizer with some decent performance might have -110 dBc/Hz phase noise at 10 KHz offset from the carrier. Plugging that into a conversion spreadsheed (gently lifted from wenzel.com), gives 462,000 fS of time jitter. Sorry, this website is not letting me upload the .xls file.

Maybe you can describe exactly what you are trying to do. A little time jitter is often desired (dithering) to guarantee an honest 16 bit performance.

 

[maniana]

I need to design a sampling clock generator for 16 bit ADC (probably LTC2209) that will sample IF in software radio. I dont want to go in details about the architecture but the ADC will not sample at a constant rate ("multistandard" receiver). Sometimes it will be GSM, sometimes just HF panorama. The concept is that the sample rate must be variable as it apparently simplifies the job of software eng. (I know little about it). I have a good GPS stabilized 10MHz and 20MHz reference. One of the methods I know to generate stable , low jitter clock is to use Nth harmonic of the reference. However this way I can get only some common frequencies , but how to get i.e. 101.23MHz (dont ask me why I need this freq, this is just an example, I received a 2 pages long list of frequencies that I have to be able to set precisely). And as I said before this can be done by soldering some components as it is on per PCB basis, but the PCB has to be universal. I figured out that doing it the way described in AN800 above is fine, however I am afraid that phase nose is still too big for a 16b ADC undersampling 300MHz IF.
One of the things I want to know is how do you generate a very low phase noise , precise frequency clock if you don't have a crystal oscillator at this frequency and the frequency is not a multiple of somithing common like 10MHz?
Good 16b performance is needed.

 

[kalyanasv]

The most important thing you want to note about the clock is the ppm error. Jitter tolerance of "fs" ouch. Its a struggle to get that in ASIC designs. Considering you have a massive budget of $50 per chip. You could try this **broken link removed**. I believe it is around...but definitely should do your job. Also make note that even thought your reference is GPS stabilized at 10Mhz, it will still have some ppm error whcih you will need to correct and errors multiply in this case so I don't think the "fs" is feasible with the budget maybe with a rubidium atomic clock..on a GPS satellite.

 

[tony_lth]

I think for fs jitter, you need use OCXO.

 

[maniana]

I have a GPS stabilized reference, stability 10e-11, ppm is not an issue here.
Let me rephrase the question:
How to generate a sample clock suitable for 160MSPS 16bit ADC undersampling 300MHz IF at 134.51MSPS (this is just an example to make sure you can't find a OCXO with f=134.51MHz) if you don't have OCXO, XO etc.. with exactly the frequency of interest ?
You only have a good 10MHz or 20MHz reference frequency.

This is just onee of the problems here.

 

[ledum]

Use AD9520-X or AD9522-X as sample clock generators with your 10MHz or 20MHz reference frequency. AD6654 | 14-Bit, 92.16 MSPS, 4 & 6-Channel Wideband IF to Base Band Receiver | Digital Up / Down Converters | Digital to Analog Converters | Analog Devices and **broken link removed** are very interesting chips. You will get your 16+ bits after resampling and DDC.

 

[biff44]

by "system engineering" I mean to go over the system specifications carefully and figure out why you need such tight specifications. For instance, you can have a DDS based synthesizer which will give you the 1 khz step size you wish for. But there will be much more than 1 fs of jitter. But since most of this jitter will be +/-, statistiaclly it will "average-out" over your ADC sample size and become less important. So you need to ask your DSP processing guy exactly why he is telling you a specification that is 1000 tighter than you can easily achieve. It sounds like the DSP guy does not know what he is doing.

Also keep in mind that if he is parallel processing multiple channels, if you are feeding each channel with the same clock jitter, it will correlate out to a much lower effective jitter (assuming the distribution time delays are ~ matched)

 

[rfmw]

1 fs ( which is crazy by the way) and $50 budget? I don't think this goes hand in hand mister. I've been working with LTC 2209 with a clock jitter of around 200-300fs (100Hz-10MHz) and I get 12.5 bits which is already on the limit of the ADC. I'd advise you ultra-low phase-noise XCO + DDS, but you'll end up with several hundreds fs of jitter.

 

[maniana]

I don't expect 1fs, I know this is not realistic, even with unlimited budget. If I can get 150fs I will be happy.
Some time ago I saw TI's presentation where they used one of their DAC to generate a clock. It apparently was better than any DDS and certainly a PLL.
Can anyone of you put a number on how much a DDS (which one ? AD9854?) is better than AD9522 or the circuit from AN800 ?

 

[rfmw]

I see that AN800 does not provide the final phase noise performance plot of the PLLed VCO. Would be interesting to see it. The AD9852 and AD9854 have good phase noise performance, comparable to the AD9522 (I keep in mind the Figure 33 in AD9522-4 datasheet). So one should make a careful design review, which solution would give better final phase noise at your requirements. Maybe a DDS used as a reference to the PLLed VCO would give you a good phase noise and small frequency step?

 

[tony_lth]

One latest article said AD product can reach 200fs, I think that's your object. And the article don't give more details about it.

 

[ledum]

20MHz ref., may be, is too low. Compare, pls. It's my real clock project for AD9230 with AD9517-0 as clock source.