Need a help for Synopsys VCS compile and Simulate....

[rakeshrupan]

HI All,

Could you tell me about how we can simulate my design in Synopsys VCS[Linux Machine]. Give me step for compile and Simulation. This very helpful to me.

Thanks,
Rakeshrupan.

 

[zjushmily]

HI All,

Could you tell me about how we can simulate my design in Synopsys VCS[Linux Machine]. Give me step for compile and Simulation. This very helpful to me.

Thanks,
Rakeshrupan.

you can use GUI or script, you can refer Synopsys VCS quick refenrence to get the information in detail.

 

[viju]

vcs -R xyz.v
you can add other switches if you are using
for verilog 2000 - vcs -R +v2k xyz.v
for system veriilgo vcs -R -sverilog xyz.v

 

[rakeshrupan]

HI zjushmily/viju,

Thanks U very much, Are u have any script for the compilation and loading in Synopsys vcs?. Give me an example.

Thanks in advance,
Rakesh

 

[HolySaint]

u can study the synopsys vcs ug carefully
wht u need is all on it

 

[rakeshrupan]

HI HolySaint,

Can u give me a Userguide for the Synopsys tool. Really help me for that.....

Thanks,
Rakeshrupan.