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NC-Verilog hdl.var problem?

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davyzhu

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hdl.var

Hi all,

I am a NC-Verilog newbie and confused with NC-Verilog's file.

In cds.lib, map logical lib name to physical location
Code:
DEFINE ic_lib /lsi_lib

Why map again in hdl.var?
Code:
DEFINE WORK worklib
DEFINE LIB_MAP (myfile.v => mylib, ./cell_lib => techlib, + => worklib)

Does "myfile.v => mylib" means compile myfile.v to mylib?
And what's "+ => worklib" mean in LIB_MAP?

Best regards,
Davy
 

aji_vlsi

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ncvlog hdl.var worklib

Hi again,

davyzhu said:
Hi all,

I am a NC-Verilog newbie and confused with NC-Verilog's file.

In cds.lib, map logical lib name to physical location
Code:
DEFINE ic_lib /lsi_lib

Yes, cds.lib is for defining LIBRARIES (as the extension says).

Why map again in hdl.var?

hdl.var --> Defines HDL Variables such as:


  • WORK
    Tool options (NCVHDLOPTS, NCELABOPTS, NCVLOGOPTS, NCSIMOPTS etc.)
    Files to library maps

Read that from a VHDL perspective - one can have several libraries and have different design units compiled to different libraries. For that you need a mechanism to associate which files go to which library.

Code:
DEFINE WORK worklib

This specifies a default WORK for you. Again little VHDL centric - VHDL needs a WORK to compile any thing. One can override this with command line -work option. Note that the "worklib" above is a LOGICAL name and that must be defined by a cds.lib to a physical directory.


Code:
DEFINE LIB_MAP (myfile.v => mylib, ./cell_lib => techlib, + => worklib)
Does "myfile.v => mylib" means compile myfile.v to mylib?

Slowly becoming a NC expert you are :)
And what's "+ => worklib" mean in LIB_MAP?

Best regards,
Davy

Any other file goes there - i..e like "*" in regular expressions, default in a Verilog case statement etc.

HTH
Ajeetha, CVC
www.noveldv.com
 
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