T
treez
Guest
hello,
Do you think the below implementation of a NAND latch is OK?
.....or will the circuit blow up if the "forbiddden" condition ever occurs?
NAND latch giving latching overvoltage shutdown protection
https://i50.tinypic.com/jpx35f.jpg
...the open collector comparator "MCP65R" comparator feeds into the latch, and the comparator trips on overvoltage.
The MCP65R comparator has an internal 1.2V reference.
SN74LVC2G00DCTR NAND gate datasheet:
**broken link removed**
Do you think the below implementation of a NAND latch is OK?
.....or will the circuit blow up if the "forbiddden" condition ever occurs?
NAND latch giving latching overvoltage shutdown protection
https://i50.tinypic.com/jpx35f.jpg
...the open collector comparator "MCP65R" comparator feeds into the latch, and the comparator trips on overvoltage.
The MCP65R comparator has an internal 1.2V reference.
SN74LVC2G00DCTR NAND gate datasheet:
**broken link removed**