N-Channel MOSFET won't fully turn off

[cberry]

I'm trying to implement a simple FPGA controlled pulldown to control another device (pull 15V/10KΩ signal down to ground to disable device). However, I'm getting 0.5mA to 1.5mA oscillations of leakage current through my MOSFET even when the gate and source are connected together (and to ground). The stated maximum on the datasheet is 0.5uA with a breakdown voltage of 50V.
**broken link removed**

I've tried a couple of models and resoldered about 15 new fets. I've also tried putting Zeners on the gate and source to limit the voltages to 5V and 20V respectively. When soldering I've had extremely fast touches (0.5s or less) on the leads to try and prevent thermal damage. I've seen that the MOSFET will sometimes work for a minute and then the leakage oscillations start.

What could be causing / allowing the current to leak through?

Thanks,
CB

 

[srizbf]

is it like M1 gate is controlled by fpga o/p pin?

and you take o/p from drain of m1 to the external device?
so that you want o/p to be at 15v or at0v .

srizbf
20thmay2010

 

[cberry]

The M1 gate would not be grounded in the real version, it would be controlled by a 3.3V CMOS FPGA output. I have the gate grounded in my current version to try and understand the leakage issue.

The 15V source, 10K pullup, and external device input (connected to the MOSFET drain) are all in the external device.

Yes, the o/p needs to toggle between 0 and 15V based on a toggling of 0 to 3.3V from the FPGA.

Thanks,
CB

 

[srizbf]

could you please check the o/p of fpga pin separately
(ie, without connecting anything to it)
and see whether it is according to the expected voltage and frequency.

what is the o/p pin configuration of the fpga concerned?

since fpgas have varieties in its o/p config ( you can program ).

srizbf
20thmay2010

 

[cberry]

The FPGA is out of the loop in the circuit I'm testing. I just have the gate and source of the MOSFET grounded and there is still ~1mA of leakage current oscillations.

It is normally configured as a 3.3V CMOS driver with no internal pulls.

 

[dick_freebird]

With the very low VT there's a chance you are in subthreshold
conduction even with Vds-0. That means any gate noise at all
will be amplified. May be that your fixture L and Miller C are the
tank.

Might try killing Q with a ferrite bead, drain resistance, etc.

 

[FvM]

You presented BSS123 in the schematic but linked a BSS138 datasheet. May it be the case, that you actually assembled a depletion type
MOSFET, e.g. BSS126? Did you very the marking?

 

[cberry]

FVM, I've tried parts:
BSS138W-7-F
and
RHK005N03T146
I verified the markings are correct. The part in the schematic was just a part that LTspice had in its library.

Mr Freebird,
I checked out sub-threshold conduction and Miller C and didn't see much I could do for my circuit. Could you further explain a practical way I could minimize the hazards you describe?

"May be that your fixture L and Miller C are the
tank.

Might try killing Q with a ferrite bead, drain resistance, etc.
"

Thanks,
Clay

 

[dick_freebird]

First I would poke around (finger, if working voltage is low
enough) and look for changes (or lack) in oscillation frequency.
You may be able to identify a sensitive node or loop.

I've seen the occasional measurement problem (oscillation)
with high current devices and long leads. Sometimes a
ferrite bead kills it. We used to bead every line in standard
test jigs, just for luck.

Adding some source resistor (less than will bother load
switching) might help denegerate the local gain. Adding a
gate series resistance could give you more negative feedback
at high frequencies (at the cost of some transient switching
loss and increased rise / fall time - not necessarily bad).

You may be stuck with raw L (wires got to go the distance)
but you can certainly degrade the Q until it quits singing,
if you can find the fat lady.

 

[cberry]

It looks like the problem was due to the relatively high pull-up voltage on the drain side and the relatively low Vgsth. The Miller Capacitance was charging the gate and causing the oscillations. The fix was to further decrease the Rg from about 1 to 2KΩ to about 200Ω and up the drive strength on my FPGA to 24mA.

This IRF document describes this effect on page 11 and 12:
http://www.irf.com/technical-info/appnotes/mosfet.pdf

Thanks,
CB

 

[FvM]

Just a another lesson not to believe in posted circuits (or whatever has been thought an equivalent
of the original problem that actually isn't.) .

You didn't say a word about a gate resistance.