My VHDL tricks collection.

[kelvin_sg]

vhdl tricks

Another VHDL arithmetic question!

Regarding signed multiplication C = A*B;
Syntax-wize NC = NA + NB, with 1 extra bit just to take care of CMAX = (-2^(NA-1))*(-2^(NB-1))?


In Verilog we use NC = NA + NB - 1 with (-AMAX)*(-BMAX) tied to CMAX-1.

 

[shnain]

vhdl tricks methodologies

my_sum <= '1' & (WIDTH_c-2 downto 1 => '0') & '1' ;

 

[kelvin_sg]

verilog tricks

My first trick..

signal	my_sum	: std_logic_vector(WIDTH_c-1 downto 0);  

...
my_sum(WIDTH_c-1) <= '1';
my_sum(0) <= '1';
my_sum(WIDTH_c-2 downto 1) <= (others=>'0');

How do I replace the above assignment with one-liner?

Thanks!

my_sum <= '1' & (WIDTH_c-2 downto 1 => '0') & '1' ;

Yeah. Thank you!

Another one..
In IF statement, how do I use "others"?
My BIT_SEL1 and BIT_SEL2 are constants..

if (my_sum(BIT_SEL1-1 downto BIT_SEL2-1) /= (others=>'0')) then
blah blah;
end if

 

[vikas_lakhanpal27]

vhdl trick

if <condition> then
.....
else ----(others)
.....
end if.

Added after 4 seconds:

if <condition> then
.....
else ----(others)
.....
end if.

 

[kelvin_sg]

bit trick vhdl

if <condition> then
.....
else ----(others)
.....
end if.

Added after 4 seconds:

if <condition> then
.....
else ----(others)
.....
end if.

It's a method.. but too complicated..
I like best is one liner..

I declare an extra variable to handle that.

 

[NanhTrang]

tricks for vhdl

Please post if you have any more tricks!!

 

[kelvin_sg]

Please post if you have any more tricks!!

I just shifted from Verilog to VHDL, so this thread is intended to ACCUMULATE
my favorite tricks.

Next Question:

Regarding parameterization..

How shall I deal with my_sig(NA downto NB) when NA == NB?
When coding with parameters, this situation can happen. In Verilog my_sig(NA downto NA) is valid.. :idea:

Added after 5 hours 30 minutes:

Regarding signed multiplication C = A*B;
Is NC = NA + NB?

Logically it should be NC = NA + NB - 1?

Magnitude = 2^(NA-1 + NB-1);
+ 1 Sign bit
= NA_NB-1?

 

[shnain]

How shall I deal with my_sig(NA downto NB) when NA == NB?
When coding with parameters, this situation can happen. In Verilog my_sig(NA downto NA) is valid.. Idea

This is also valid in VHDL

Enjoy!

 

[vikas_lakhanpal27]

Good work going!