thakur.umesh
Newbie level 3
Dear Experts ,
Iam into a designing of core IP and sucessfully completed it using verilog
and functional verification is done using Modelsim se 6.0.
My IP core has 5 main modules of which I synthesized 1 module using xilinx ISE 8.1i demo version
and the gatecount was something around 122k
Now i want to synthesize the whole code..and i guess the gate count would be in lakhs
AS my target is to go for FPGA prototyping....(porting on to FPGA)
(Iam working on windows xp platform)
--
Regards
Umesh [/b]
Iam into a designing of core IP and sucessfully completed it using verilog
and functional verification is done using Modelsim se 6.0.
My IP core has 5 main modules of which I synthesized 1 module using xilinx ISE 8.1i demo version
and the gatecount was something around 122k
Now i want to synthesize the whole code..and i guess the gate count would be in lakhs
AS my target is to go for FPGA prototyping....(porting on to FPGA)
(Iam working on windows xp platform)
--
Regards
Umesh [/b]