My code doesnt work in post synthesis

[thetrice]

artimitum salzhar.

 

[TrickyDicky]

did you run it through timing analysis? can it run at 25 Mhz like you're tasting with?

 

[thetrice]

did you run it through timing analysis? can it run at 25 Mhz like you're tasting with?

timing analysis says it can run at 180 MHZ i tried running it even at 5 MHZ but it give an output in post route simulation , behavioural works fine though.
and as u can see in the code , the fpga doesnt do anything except take input and get it out from output .. thats it. And i dont know where is the problem.

 

[FvM]

I wonder what's all the FSM stuff for? Or is the code intended as a model for something else? The two modules can work fine with one clock period pipeline delay each by just cascading them.

the fpga doesnt do anything

In any case, the post synthesis simulation can show you what's "not working" in detail.

 

[thetrice]

I wonder what's all the FSM stuff for? Or is the code intended as a model for something else? The two modules can work fine with one clock period pipeline delay each by just cascading them.


In any case, the post synthesis simulation can show you what's "not working" in detail.

The model is a simplified model of a much bigger model , i simplified it in hopes to find the error,All i have after behavioral simulation is post-translate simulation which doesn't show where the error is ?
View attachment simulation.bmp
Simply if i know why the timing error appears although everything in my code works at rising edge of the clock ...