doenisz
Junior Member level 2
I have an RF energy harvester chip that I am testing at the moment. To control the charging (sleep) of a storage capacitor and the active period where it is connected to the communication/digital blocks; I use an hysteresis comparator. I test it currently without connecting the rectifier output to the rest of the system to verify the latter. So, I provide DC voltage by myself as if it's the rectifier output, which powers up a charge pump that's connected to a storage capacitance.
Under normal operation, the voltage on the storage capacitor looks something like this (yellow on oscilloscope screen):
Normal operation
As you can see, after it reaches a certain voltage, the communication signals (green and blue on the above figure) gets triggered, discharge the storage capacitor, and after a while, we return back to charging.
Now, I have observed two very interesting phenomena during the testing:
2) If I lift my board and cut its contact with the ESD mat, the voltage on the storage capacitance keeps rising but the hysteresis comparator does not trigger; so communication period cannot be activated.
Bottom of my board looks like this, so the solders do touch the ESD mat during the operation.
Bottom of the test-boards
3) Same behavior in (2) happens if I lift the box in red in the below figure, even when the board is in contact with the ESD mat:
Box surrounding the antenna and the die
This box is just for protection because the die is wirebonded with chip-on-board process.
My thinking for (2) and (3) is as follows:
In this current testing, the output of the rectifier, which will normally be connected to the rest of the chip is floating. This rectifier output is one pad of the chip and another pad of the chip takes a DC voltage that powers up the rest of the chip. For testing and debugging purposes, they are different pads, and in normal operation, I simply short them with a jumper; but in this particular test, I give a DC voltage externally to the second pad, while the rectifier output is floating.
The antenna is designed to be matched to the rectifier when there is no chip cover, so when I lift the cover, I may be establishing the matching, which would increase the rectifier output even more; hence disturb the operation, even when the board touches the mat.
So, maybe this accumulated voltage on the floating pad is what is disturbing my operation? When the board touches the MAT, this accumulated charge can simply go away. I cannot see physically, how the presence of that signal would disturb the rest of the chip, though.
What may be the reasons for these things that I am observing?
Any input is appreciated.
Under normal operation, the voltage on the storage capacitor looks something like this (yellow on oscilloscope screen):
Normal operation
As you can see, after it reaches a certain voltage, the communication signals (green and blue on the above figure) gets triggered, discharge the storage capacitor, and after a while, we return back to charging.
Now, I have observed two very interesting phenomena during the testing:
- The discharge/communication period was initially very short. It was only after I connected the ESD mat itself to the ground by hooking it up to an oscilloscope probe that it started acting as it should.
2) If I lift my board and cut its contact with the ESD mat, the voltage on the storage capacitance keeps rising but the hysteresis comparator does not trigger; so communication period cannot be activated.
Bottom of my board looks like this, so the solders do touch the ESD mat during the operation.
Bottom of the test-boards
3) Same behavior in (2) happens if I lift the box in red in the below figure, even when the board is in contact with the ESD mat:
Box surrounding the antenna and the die
This box is just for protection because the die is wirebonded with chip-on-board process.
My thinking for (2) and (3) is as follows:
In this current testing, the output of the rectifier, which will normally be connected to the rest of the chip is floating. This rectifier output is one pad of the chip and another pad of the chip takes a DC voltage that powers up the rest of the chip. For testing and debugging purposes, they are different pads, and in normal operation, I simply short them with a jumper; but in this particular test, I give a DC voltage externally to the second pad, while the rectifier output is floating.
The antenna is designed to be matched to the rectifier when there is no chip cover, so when I lift the cover, I may be establishing the matching, which would increase the rectifier output even more; hence disturb the operation, even when the board touches the mat.
So, maybe this accumulated voltage on the floating pad is what is disturbing my operation? When the board touches the MAT, this accumulated charge can simply go away. I cannot see physically, how the presence of that signal would disturb the rest of the chip, though.
What may be the reasons for these things that I am observing?
Any input is appreciated.