nge
Junior Member level 1
How can I design MUX/DEMUX on bidirectional port? It doesn't seem right. Any help would be great. Thanks
Code:
entity MUX_DEMUX is
generic (n : integer);
port (
a : inout std_logic_vector(n-1 downto 0);
b : inout std_logic_vector(n-1 downto 0);
o : inout std_logic_vector(n-1 downto 0);
s : in std_logic_vector(1 downto 0));
end MUX_DEMUX;
architecture simple of MUX_DEMUX is
begin
process(s,a,b)
begin
case s is
when "01" => o <= a;
a <= o;
when "10" => o <= b;
b <= o;
when others => o <= (others=>'0');
end case;
end process;
end simple;