JAMR
Newbie level 3
Hello all.
I've been working on a project of controlling an LCD from a PIC through a Lattice CPLD. The PIC code is fine but I keep getting garbled info when outputting through the CPLD. It appears that the issue is not being able to send data back to the PIC. I am unable to get my bidirectional ports to work correctly.
Any help is appreciated.
Thanks - Not a homework project
I've been working on a project of controlling an LCD from a PIC through a Lattice CPLD. The PIC code is fine but I keep getting garbled info when outputting through the CPLD. It appears that the issue is not being able to send data back to the PIC. I am unable to get my bidirectional ports to work correctly.
Any help is appreciated.
Thanks - Not a homework project
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 module U3_CPLD_GPIO( //Port List CPLD_CLK , CPLD_RESET , PMAD , PMCS0 , PMRD , PMWR , LCD_BL , LCD_E , LCD_RS , LCD_RW , LCD_D , PMD , INT1 , INT2 , IO_DIR , LED ); //Input declaration input CPLD_CLK; input CPLD_RESET; input PMAD; input PMCS0; input PMRD; input PMWR; //LCD output LCD_BL; output wire LCD_E; output reg LCD_RS; output reg LCD_RW; //LCD IO Config //reg pcu_rnw; direction (read=1 or 0= write); reg [7:0] WriteData; inout wire[7:0] PMD; //LCD data to/from PIC //input IO_DIR; // Direction of io, 1 = set output, 0 = read input //assign PMD = (pcu_rnw)? 8'bz : WriteData; //reg pcu_rnw2; direction (read=1 or 0=write) inout wire[7:0] LCD_D; //Data to/from LCD //assign LCD_D = (pcu_rnw2)? 8'bz; //INT output INT1; output INT2; input [3:0]IO_DIR; //LED output reg LED; //Port Master Signals reg [7:0] PMD_Regd; reg [7:0] PMD_Out; reg PMWR_Regd; reg PMRD_Regd; reg PMCS0_Regd; reg PMAD_Regd; assign LCD_BL = 1'b1; //LED Blink reg [25:0] counter; always @(posedge CPLD_CLK) if (counter == 4000000) //4MHz begin counter <= 0; LED <= ~LED; end else begin counter <= counter + 1; LED <= LED; end //LCD Process always @(posedge CPLD_CLK) if (PMWR == 1'b0) begin PMD_Regd [7:0] <= PMD [7:0]; PMWR_Regd <= PMWR; PMRD_Regd <= PMRD; PMCS0_Regd <= PMCS0; PMAD_Regd <= PMAD; //LCD_E LCD_RS <= PMRD_Regd; LCD_RW <= PMWR_Regd; LCD_E <= PMAD_Regd; #20; LCD_D [7:0] <= PMD_Regd [7:0]; end else begin //pcu_rnw2 <= 1'b1; //set to input from LCD //WriteData <= LCD_D; //read from LCD to WriteData //pcu_rnw <= 1'b0; //output to PIC //PMD = WriteData; //PMWR_Regd <= PMWR; //PMRD_Regd <= PMRD; PMD_Regd [7:0] <= LCD_D [7:0]; PMD [7:0] <= PMD_Regd [7:0]; end endmodule