multiplication in verilog

[magnanimus]

hey
I am a student of B-tech . I am doing a project in which i have to use a parallel multiplier. I have to multiply two matrices of 8x8 size and each element is a 16 bit fractional number represented in binary format. I wrote a code in matlab and verilog both but when I matched the result of verilog with matlab, I found big difference between the two results.
Can someone help me getting precision in multiplication in verilog ?????
:?: :?:

this is the module that i am using in verilog code for multiplying a row and a column of two matrices ..........

module multiply(p,d0,d1,d2,d3,d4,d5,d6,d7,b0,b1,b2,b3,b4,b5,b6,b7);
output reg [31:0] p=0;
input [15:0] d0,d1,d2,d3,d4,d5,d6,d7;
input [15:0] b0,b1,b2,b3,b4,b5,b6,b7;

always @(d0,d1,d2,d3,d4,d5,d6,d7,b0,b1,b2,b3,b4,b5,b6,b7)
begin
p=d0* b0 + d1* b1 + d2* b2 + d3* b3 + d4* b4 + d5* b5 + d6* b6 + d7* b7;
end
endmodule
I have a separate top module for instantiating this module

As the numbers are fractional so i am having trouble in handling that.
If anyone knows anything about fractional number multiplication in matlab then please give your wise suggestion to me.....

 

[fcfusion]

1) If you're using fractional numbers I assume this includes negative numbers right?

you should declare the inputs as signed:

input signed [15:0] d0,d1,d2,d3,d4,d5,d6,d7;

2) I have some serious doubts that you can multiply two registers just like that. It generally requires an hardware multiplier which is an hard thing to do, especially for floats.

What you can do is load this values into float variables and make whatever operations you want using them. That way your simulations will give no problems but you won't be able to synthesize it into a digital circuit.

You said you have to use a parallel multiplier. Are you talking about using a chip, software, or do you have to design the parallel multiplier yourself?

 

[magnanimus]

1) If you're using fractional numbers I assume this includes negative numbers right?

you should declare the inputs as signed:

input signed [15:0] d0,d1,d2,d3,d4,d5,d6,d7;

2) I have some serious doubts that you can multiply two registers just like that. It generally requires an hardware multiplier which is an hard thing to do, especially for floats.

What you can do is load this values into float variables and make whatever operations you want using them. That way your simulations will give no problems but you won't be able to synthesize it into a digital circuit.

You said you have to use a parallel multiplier. Are you talking about using a chip, software, or do you have to design the parallel multiplier yourself?

hey thanks for replying
actually i am using the concept of parallel multiplication in which in each cycle one row of a matrix is multiplied with each column of the second matrix....so in next cycle the next row with all the columns of the second matrix thus it reduces the computation complexity..............
.............. i am doing a project on image processing in which i have to design a 16 bit multiplier....... i have to implement this on spartan3E FPGA
i am using fixed point representation for this...... all the numbers i have are fractional ....and i don't know how to tackle with the fractional numbers...
If u have any idea how to multiply two fractional numbers in verilog then please guide me.... :| :|

 

[fcfusion]

If you're using a Spartan3E, that will make your job a lot easier since that FPGA come with several built in 18x18 bit hardware multipliers. You should check the FPGA's datasheet to see if you model has enough multipliers to parallelize all your multiplications.

At least you won't have to create an hardware multiplier.

The code you used to multiply registers is only valid for unsigned integers.

Multiplying fractional numbers is a bit more dificult, and you'll have to choose if you're going to represent your number in floating point or fixed point.

Probably you should use fixed point since it is easier. See this topic, it might help you:

 

[nir_kumar21]

Can anyone post code of matrix multiplication in verilog...for 32 bit??

Thanks