multiple feedback VCO

[khorlipmin]

My VCO is a triple feedback type. the feedback consisted of three pairs of NMOS in the feedback path.
How do I size them? any ratio in particular? I know they should not be the same as the reason for using multiple feedback is to increase the oscillation frequency. if all are of the same size, the frequency will acutually reduced. what is the theor behind this? please enlighten me.

 

[Youncen]

I am interested in it too,I had seen this circuit in some paper, but don't remember now,will you please tell me the paper name?

 

[jfyan]

My VCO is a triple feedback type. the feedback consisted of three pairs of NMOS in the feedback path.
How do I size them? any ratio in particular? I know they should not be the same as the reason for using multiple feedback is to increase the oscillation frequency. if all are of the same size, the frequency will acutually reduced. what is the theor behind this? please enlighten me.

hi khorlipmin,
you can write out the oscillation frequency in this way:
first, find out the main loop, eg, there are four stages in the main loop,
and then, to the delay cell, you also can calculate its transfer fuction, that is H(s)=
vo(s)/vi(s), of course, you must specify the output and input,as to the cell in your figure, the output is very clear, but there are three inouts, so you can assume one of them is the vi(s), and the others can be defined as vi(s)*(exp(jphi)...
so far, you can finish the transfer fuction H(s).
at last, you can find the oscilation frequency in the term of input transistors gm, and size them.
plz, note that the phase between the inputs must be specified from the connection of the osillation circuit.
another strong suggestion is you can refer to the jssc paper:

A 1.25-GHz 0.35-μm monolithic CMOS PLL based on a multiphase ring oscillator.
Volume 36, Issue 6, June 2001 Page(s):910 - 916.
after reading the above paper, you will be enlightened further.
may it help.
jeff.yan

 

[khorlipmin]

thanks for the paper, will look into it and come back to u later

 

[khorlipmin]

I still could not obtain higher frequency with multiple feedback. I assume that the idea behind this is that with all other variable remain the same, with proper sizing the multiple feedback will provide higher frequency? am i correct? Or should I be increasing the biasing current when i am using triple feedback? if this is the case why not i just increase the current at the single loop oscillator? it can give even higher frequency at the same biasing current.

 

[jfyan]

I still could not obtain higher frequency with multiple feedback. I assume that the idea behind this is that with all other variable remain the same, with proper sizing the multiple feedback will provide higher frequency? am i correct? Or should I be increasing the biasing current when i am using triple feedback? if this is the case why not i just increase the current at the single loop oscillator? it can give even higher frequency at the same biasing current.

hi,
another isscc paper i can suggest is
"cmos current-control oscillators using multiple-feedback-loop ring architechtures",
isscc97,pp386-387.
i remember the osc-ckt is almost same to yours. i don't know whether your design is just imitating the paper. if not, you can check your ckt's connection with the paper's.
of cource, there are other forms to the same idea.
as for your question, plz check the connection further,because the different feedback has different osc-frequency,which may be faster or slower.

good luck.
jeff.yan


yes, you r right, i think, we needn't in

 

[khorlipmin]

Yes I am imitating that topology at first. Yet there is slight difference which I think might have made my circuit not working. Thus I am now redesign using the concept of the first paper you recommended and it works!
Main idea is I need to use five stages for dual feedback making i=3; and a seven stage for triple feedback, taking i=3 and i=5. Have tested the dual input now designing the triple input. cheers!
thanks a lot