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multiple bjt switch circuit interpretation

yefj

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Hello,there is an intresting structure shown bellow, i can that there is a form of switch being used.
from mosfet i know that Vgate above Vt opens the transistor.
But here the bjt's are in weird forms .
how can i interpret the logic of this circuit?
Thanks.


1620677067049.png
 

KlausST

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Hi,

I'd say it's meaningless to talk about a circuit that misses:
* supply voltages
* input voltage levels
* a lot of part values
* load conditions

Klaus
 

FvM

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What do you mean with "the bjt's are in weird forms"? Apart from missing information about voltage levels and part values it's a useful circuit.

E.g. Q3 is turned on by R6 when Q2 is off and off when Q2 is on.
 

yefj

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Hello,i am trying to understand the functionality of the first part.
first I have picked an PNP transistor as shown bellow,It has the following caracteristics of Vbe sweeps.
then i tried to simulate the first part of the circuit shown bellow.
I know that this is a floating point protection connection but what to connect to the collector in order to simulate the floating input?
I also dont know what what is a floating point voltage.

Thanks.
1620845912376.png


1620845937451.png
 
Last edited:

FvM

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Why did you simulate a completely different circuit? Originally, pnp transistor emitter is connected to 3V. Collector is driving a grounded resistor.
 

BradtheRad

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Your initial schematic looks as though its supply is positive polarity. Shown below is conventional usage of PNP (in common emitter operation).
My schematic flips the PNP icon so that its arrow points downward. The arrow indicates the direction of a PN junction, therefore direction of current flow from positive to negative.

PNP usage with positive supply bias comes fm pot load to 0V ground.png
 

KlausST

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Hi,

The circuit (upper of post#5) is called "high side open collector"
* "high side" because it is switching the positive (high) supply voltage (+3V) instead of GND.
* "open collector" because the collector is the output....and it's left open ... so the end user may connect whatever he wants to this output.

Example: This often is used by transistor outputs of Siemens PLCs. Siemens leaves the output open ... for the end user to connect a LED, a buzzer, a relay....

Klaus
 

yefj

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Hello Klaus,i am used to work with mosfets.
in mosfet we have Vgs>Vt to open or close and Vdg>Vt to see the formula of the biased current going threw the transistor.
I tried to read the following tutorial but i dont have this innecquality conditions in PNP .
What the the voltage innequality conditions so i could see exactly if its open or closed and what current goes threw the PNP ?
Thanks.

1620934547403.png
 

KlausST

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Hi,

All the tutorial circuits show resistors. Yours not. Add them.

Mind V_BE polarity

Switch open --> no current flow
Switch closed --> current flow

Klaus
 
Last edited:

yefj

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Hello ,I have updated the circuit as shown bellow.
i am looking for explanation that shows PNP as if its a mosfet.
I want to know what voltage /current innequality should i use so i will know that PNP is OPEN.
and in what state ,(in mosfet its linear or saturation) so i know the exact formula of the current that goes threw.

1620943787515.png
 

KlausST

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Hi,

A BJT never can work the same as a MOSFET.
A BJT has different states with different operation modes.

Why do you refer to an internet page with explanations, but neither use the example circuits ... nor use the given math?
What should I do now? Copy the pictures and the text?

Please ask a clear question with the terminology given in the internet.
Please also give an example you want to calculate with all known voltages and currents.

Klaus
 

yefj

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Hello Klauss ,i understood the first of all i need to keep Ve>Vb and Vb>Vc to keep the holes flowing in active mode as shown bellow.Vbe is negative to keep EB forward biased(to allow) the flow of holes.

regarding what BradtheRad said My R2 is supposed to close the transistor when In is flowting.
But i cant see how exactly.
When we put this resistor we make some voltage divider Between VDD_3 and V_in,
so If V_in is low Vb is between 3V and 0 and our Emitter based junction is forward biased which is great.
but if the collector will be at low voltage also then base collector junction will also be reversed biased and the holes will continue to flow
i cant see how this R2 resistor closes the flow of current?

if collector is lower then base we will have all the conditions for the hole current to flow from emitter to collector .
Where did i go wrong?
How do we know what is our collector voltage ?the collector goes into the circuit.
I dont know what collector voltage should i put so R2 will prevent current flow when Vin is floating.
Thanks.

1621006494018.png

1621004693605.png

--- Updated ---

UPDATE:
Yes :) i understood the principle when there is no voltage and the Vin is floating the there is no current
and emitter voltage will be the base voltage SO Vbe=0 thus EMITTER BASE juction will not be forward biased thus transistor is off and no current flow.
--- Updated ---

second UPDATE:
So for the first step We need to have Vb>Vc so the base collector juction will be reversed biased.
Our Vb is a voltage divider between 3V and Vin(which is 0)
So we get some collector voltage lower then Vb,this collector voltage goes to the next step shown in the arrow bellow and meets R4.Q6 is an NPN transistor and we need Vb>Ve and Vc>Vb to have base emmiter junction forward biased and base collector junction reverse biased(flow from P to N is aforward biased no matter is its electrons of holes)

Why do we need the R4 resistor between the biasing voltage and the base connection, why cant we just plug voltage into the base(like they do in Q4)?
Thanks
1621009533703.png
 
Last edited:

KlausST

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Hi,

Please confirm: "vdd_3" means "+3V"
Also mind that on schematic usually the most positive supply is on top and the most negative supply is on bottom af a sheet.
So +3V should be on top, GND on bottom. Your PNP symbol should be rotated that emitter is on top, collector on bottom, base on left.
(refer to the schematics of the tutorial)


Now let´s focus on the PNP. All voltages are negative to the voltages of an NPN.
So let´s be correct and use negative values.
Also note:
* V_BE is the between base (+, when you use a voltmeter) and emitter (-)
* V_B is the voltage of base (+) referenced to GND (-)
* V_R is the voltage across a resistor. (sadly hard to define an orientation)

Now let´s focus on your schematic of post#13. (Sadly it misses a GND symbol and it misses a circuit at the collector: like a resistor connected to GND for example)

R2 is good to have, but not essential. It´s in the schematic, so let´s use it...

basic PNP operation: (simplified)
When V_BE is 0V ... -0.5V --> no base current, no collector current, switch is considered OPEN
When V_BE is -0.5V ... -0.7V --> increasing base current. if there is a suitable circuit then there will be collector current.
When V_BE is -0.7V ... and more negative --> high base current, you need to limit it with a resistor (R1), high collector current. Switch is considered CLOSED
(depending on transistor type the exact voltages vary)

in any case:
* V_BE will be V_R2
* I_R1 = I_B + I_R2

__OPEN__
if "in" is not connected then V_BE should be about zero. Here the benefit of "R2": it ensores the voltage is very close to to zero, thus it ensures the switch is OPEN.
the voltage at the unconnected "in" node will become +3V.
So you are free to leave "in" unconnected or connect it to +3V

__not OPEN__, __not CLOSED__
to drive V_BE to -0.5V you need to have 0.5V across R2... still no base current, thus I_B1 = I_B2 (simple voltage divider)
thus you need to have 5k/1k * 0.5V across R1 = 5 X 0.5V = 2.5V
absolute voltages: At base: 3V - 0.5V = 2.5V
at "in": 2.5V - 2.5V = 0V.

What does this mean:
Even if you draw the "in" to GND there will be no meaningful collector current. The switch still is OPEN (at least at the edge)

You have a simulatin tool. So it´s time to play around.....
Vary "in" voltage from 0 to 3V and see how base current, base voltage collector current vary...

Later we do the "CLOSED" situation.

Klaus
 

yefj

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Hello Klauss, i have simulated the circuit with both negative and positive Vbe as shown bellow.
As you said with negative Vin voltage we get highest current our Vemiter-Vbase is negative so the EB junction is foward biased.
When we have Vin -1 and collector is ground so we have voltage divider between 3 and -1, Vc>Vb so base collector junction is revesve biased and we have high current.
And as you said that the Vbe plays a role in the flow of current into the transistor making the EB junction more or less forward biased if i got the idia correctly.

If i got the idia correctly could you please say what is the name of the circuit shown in the end?
Its a bjt with a diode between base emitter and a resistor between collector and base.
Very hard circuit i cant understand the idia of it,and i dont know what is the name so i could try and google it.
Thanks.

1621022115854.png

1621022679060.png


1621023672703.png
 

KlausST

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Hi,

You are not cooperative, don't answer questions, don't confirm my doubts, don't follow my recommendations.
I hope you don't mind when I leave now.


i have simulated the circuit with both negative and positive Vbe as
No, not "Vbe"
But "V_in"


our Vemiter-Vbase is negative
No, "Vemiter-Vbase" is posititive.
V_BE is negative.

No,
Vb > Vc

what is the name of the circuit shown in the end?
It is an emitter follower.
R8 makes the base high, thus makes the output high.
R8 limits base current
R8 limits Q4 collector current.
D is probably a doubtful (because not current limited) way to discharge the output.

Good luck

Klaus
 

yefj

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Hello Klauss,Sorry i thought i did follow your instruction,i will try and read again and simulate again by your instructions.
Yes "vdd_3" means "+3V.
Yes the simulation needs the collector to be connected to GND
 
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yefj

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Hello Kluass i have tried again as following:
OPEN state:
Vin=-1 Vbe=2.33-3=-0.67<0
Vbc=2.33-0
1621098858741.png


NOT OPEN NOT closed:
Vin=0
You are correct that the base current decreased down by 100 times.
looking at the datashhet bellow i could not find the table where they say that we need Vbe<-0.5 to have base current flow.
How could you see the point at which base current will be zero?
You said that base voltage is desided by voltage divider between 3V and 0V.
How could you assume in advance that I_b=0?
Also in the data sheet table shown bellow there is no Table for negative Vbe its all positive.
Where did i go wrong?
Thanks.

1621101374704.png
Thanks.
1621099551610.png
 

KlausST

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Hi,

Interesting how you interprete what the tutorial and what i wrote.

Example:
From post#
When V_BE is 0V ... -0.5V --> no base current, no collector current, switch is considered OPEN
How does this meet your "OPEN state" condition?

I'm not patient enough...

Klaus
 

yefj

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Hello Klaus ,i have tried to simulate the emitter follower .by your guidance and datasheet i have tried to swith on and off 30V.
I get Vout=Vin behavior.
Where di i go wrong?
Why its not Switching 30V on and off?
Thanks.
1621105594916.png
 

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