Multicycle vs Pipeline

[sarathbc2002]

multi-cycle pipeline

Multicycle vs Pipeline

I am confused in choosing between Multicycle or Pipeline in implementing
a chunk of logic ..I have explained the 2 possible scenarios below

PIPELINE

Below c1 through c4 are blocks of combinational logic.
"|" is a register:
A pipeline separates multiple states of combinational
logic with registers
Each block plus register will perform at 10 ns clock boundaries.
I constrain the design for 10 ns clock

in -- | c1 | c2 | c3 | c4 | -- out


MULTICYCLE

In Multicycle path I remove the internal registers

in -- | c1 c2 c3 c4 | -- out

Since the pipelined design ran at 10 ns, this
one should be able to run at 40 ns. So I constrain it with
a multicycle of 4


Are these 2 implementations functionally same ??
What is the throughput in the above 2 cases ?

In the Pipelined approach apart from the initial latency ,result is got
once every clock cycle .

In the multicyle approach I have the result once every several clock cycles

Can the throughput of multicyle be made equal to that of pipelined approach
if it satisfies certain hold constraints

 

[incisive]

pipelined versus multicycle

in the above multicycle path o/p comes out after 4 clk cycles as expected wrt pipeline 2 clk cycles here the through put varies.