hi,i want to do a multibuses affectation but it didn't work
this is my program:
TYPE data_port IS RECORD
en : STD_LOGIC;
write : STD_LOGIC;
internal : STD_LOGIC;
sel_dcache : STD_LOGIC;
sel_ram : STD_LOGIC;
sel_ext : STD_LOGIC;
addr : data_addr;
data : data_bus;
END RECORD;
entity multi is
in : inout data_port;
out1 : inout data_port;
out2 : inout data_port;
switch : in std_logic
);
architecture rtl of multi is
process(switch)
begin
if switch='1' then
out1<=in;
else
out2<=in;
end if;
end process;
end rtl;
Keep VHDL syntax rules.
E.g.:
- Add necessary library definitions.
- Define a package for the record type.
Code:
library ieee;
use ieee.std_logic_1164.all;
package defs is
-- your type definitions used in the below entity port
end package defs;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.defs.all;
entity multi is
--
end;
architecture rtl of test is
--
end rtl;
There are some additional detail errors, you'll be aware of, when the overall syntax is correct.
hi,
thanks for responding, and sorry because i don't mention that i already put all library and package.my problem is that my program didn't work when i simulated it on modelsim.