ramzitligue
Member level 1
multibuses in vhdl
hi,i want to do a multibuses affectation but it didn't work
this is my program:
TYPE data_port IS RECORD
en : STD_LOGIC;
write : STD_LOGIC;
internal : STD_LOGIC;
sel_dcache : STD_LOGIC;
sel_ram : STD_LOGIC;
sel_ext : STD_LOGIC;
addr : data_addr;
data : data_bus;
END RECORD;
entity multi is
in : inout data_port;
out1 : inout data_port;
out2 : inout data_port;
switch : in std_logic
);
architecture rtl of multi is
process(switch)
begin
if switch='1' then
out1<=in;
else
out2<=in;
end if;
end process;
end rtl;
what can i do ?thanks.
hi,i want to do a multibuses affectation but it didn't work
this is my program:
TYPE data_port IS RECORD
en : STD_LOGIC;
write : STD_LOGIC;
internal : STD_LOGIC;
sel_dcache : STD_LOGIC;
sel_ram : STD_LOGIC;
sel_ext : STD_LOGIC;
addr : data_addr;
data : data_bus;
END RECORD;
entity multi is
in : inout data_port;
out1 : inout data_port;
out2 : inout data_port;
switch : in std_logic
);
architecture rtl of multi is
process(switch)
begin
if switch='1' then
out1<=in;
else
out2<=in;
end if;
end process;
end rtl;
what can i do ?thanks.