kommu4946
Member level 4
Hi,
i have seen example code for multi cycle path in below link.
https://www.edaboard.com/threads/333626/
i am trying to understand multi cycle path implementation using above code in vivado.
i used clock as 50 mhz. i got the following timing report
here i got the data path delay as 0.908ns which is still less than one clock cycle of 50 mhz clock.
should i declare multicycle path constraint even though it is not exceeding more than one clock cycle ? i studied about multicycle path constraints which states that if the combinational delay is more than one cycle delay it is should be declared as multi cycle path
Regards
i have seen example code for multi cycle path in below link.
https://www.edaboard.com/threads/333626/
i am trying to understand multi cycle path implementation using above code in vivado.
Code:
module mc_test(
input wire board_clk,
input wire rst,
output reg [3:0] ff_1,
output reg ff_2
);
clk_wiz_0 pll
(
.clk_in1(board_clk),
.clk_out1(clk));
reg [1:0] cntr;
reg [8:1] lfsr;
always @ (posedge clk) begin
if (rst) begin
cntr <= 0;
end else begin
cntr <= cntr +1;
end
if (rst) begin
lfsr <= 1;
end else begin
lfsr <= {lfsr[1], lfsr[8], lfsr[7]^lfsr[1], lfsr[6]^lfsr[1], lfsr[5]^lfsr[1], lfsr[4:2]};
end
end
// multicycle registers
always @ (posedge clk) begin
if (cntr == 2'd3) begin
ff_1 <= lfsr[4:1];
ff_2 <= ff_1;
end
end
endmodule
i used clock as 50 mhz. i got the following timing report
here i got the data path delay as 0.908ns which is still less than one clock cycle of 50 mhz clock.
should i declare multicycle path constraint even though it is not exceeding more than one clock cycle ? i studied about multicycle path constraints which states that if the combinational delay is more than one cycle delay it is should be declared as multi cycle path
Regards