Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

msp430 cycle time problem

Status
Not open for further replies.

steve.hunch

Member level 1
Joined
Mar 8, 2011
Messages
40
Helped
8
Reputation
18
Reaction score
7
Trophy points
1,288
Location
Australia
Activity points
1,478
Hi ,
I use eval board "LaunchPad" I set CLK to 1MHz.
When I try to check the maximum on-off rate on one of the pins I get 10usec - 100KHz.
Doing just:

while(1)
{
P1OUT = 0;
P1OUT = 0xff;
}


The problem is that system clock is 1MHz, but this code gives my only 100kHz.
What can be a problem?

Changing clock to 10MHz, I get 1MHz at the I/O.
 

If you disassemble this C program into Assembly code, maybe will obtain the answer.
Each instruction and statement of code execute specific funcion and consumes instruction time.

+++
 

I did this, but apparently each each of those instructions disassembles to one assembler instruction. This means that I should get, at least for logical '0' approximate 1usec time (with 1MHz system clock).
But I still get 10usec. There is some factor of 10 in instruction execution...
 

while(1) -> Instruction that compare, and skip
{
P1OUT = 0; --> instruction that set output
P1OUT = 0xff; -> instruction that set output
} -> instruction that jump

Maybe there are other operations.
Try change optimization options.

+++
 

No .. actually you are getting a good toggle speed on you output, but for sure with no 50% duty-cycle. Toggling a port on MSP430 does not take 1 instruction cycle. It can take 3 to 5 cycles, dpending from where your data is coming, and you got the added jump cycle from your while (i think that takes 3 cycles). Some other architectures have some special pin manipulation hardware. Always read the manual :) before chosing your architecture.. i always tell that to people that thinks that one architecture is perfect (as many does with ARM as an example). With a 50% duty cycle you would have to use xor instruction, and that woud take a total of 14 cycles for a full positive and negative edge. 3 from jump, and 4 from xor. There is no optimization that can handle hardware limitation.

Cya and GL
 
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top