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moving from 65nm to 40nm tech

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rocking_vlsi

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Hi

Moving from 65nm to 4onm or to 28nm. How it will effect in RTL design and synthesis?

What extra care need to be taken?
 

shaiko

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In general, geometry reduction allows faster devices and better power consumption (due to lower gate capacitance and shorter distances). This brings lower combinatorial delays.
For example:
A = B * C + D
This combinatorial function (when implemented with exactly the same logic) will take less time to complete with 40nm then with 65nm (and even lesser with 28nm).
 

rocking_vlsi

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Thanks shaiko:
Do you mean we will be able to synthesize same design for higher frequency at 28nm ?

Do we really care about how big combo (number logic levels) we are writing in RTL Design?
 

shaiko

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Do you mean we will be able to synthesize same design for higher frequency at 28nm ?
yes.
Do we really care about how big combo (number logic levels) we are writing in RTL Design
Of course. Each combinatorial level has a delay. Whithout resulting to pipelining, you can only do so much before you get into timing violations.
So, lowering the combinatorial delay (one of the benefits of geometry reduction) is always good.

Example:

Y = ( A * B ) + ( C * D )

When done single step (without pipelining) on a 65nm device - the result may be ready after 200ns.
When done single step (without pipelining) on a 28nm device - the result may be ready after 100ns.
 

OhaAmo

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pure RTL design shouldn't care about the process.
Of course that process change will introduce timing changes that will effect RTL design.
 

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