[Moved] what are the basic things to be for designing a buffer ?

[karthik.venkata2020]

i am doing my MS project in physical design domain , i was supposed to design a buffer cell .Can any body tell me what are the basic to be known for designing clock buffer ?

 

[doraemon]

Hello!

1. What is an MS project? I mean what is MS?
2. What is a buffer cell? I know what a buffer is, but sorry, a buffer cell....
3. What is a clock buffer? Similarily I know what a clock is, what a buffer is, but a clock buffer....

Please be more accurate if you want replies.

Dora.

 

[jayanth.devarayanadurga]

I think MS means Master of Science.

 

[FvM]

M.S., I presume means master of science.
The post would make sense in the Analog IC Design or possibly ASIC Forum.

 

[karthik.venkata2020]

M.S., I presume means master of science.
The post would make sense in the Analog IC Design or possibly ASIC Forum.

Hello sir,

sorry for asking unclear question, here i explain them
MS means Master of Science , It is equivalent to M.Tech degree.
I am doing it in the field of VLSI.

Buffer in the sense , it is also a standard cell like AND,NAND,NOR etc. So , i have mentioned
like buffer cell.

up to my knowledge we use clock buffers for clock path optimization and clock tree routing in cts stage of vlsi P&R flow
and normal buffers for data path optimization in vlsi P&R flow.

The thing is that i know how to make use of them in P&R flow , but i don't know how to design a buffer?
But as a part of my MS project i need to design a buffer ?
can any body help me out with your suggestions ?

 

[alam4vlsi]

Hi Karthik,

Actually clock buffers are predefined in libraries. During P&R flow, we just link that libraries. I guess you have to design a library for Clock Buffer which has equal rise time fall times with different drive strength.

Thanks,
Alam

 

[karthik.venkata2020]

Hi Karthik,

Actually clock buffers are predefined in libraries. During P&R flow, we just link that libraries. I guess you have to design a library for Clock Buffer which has equal rise time fall times with different drive strength.

Thanks,
Alam

hello sir,

Actually i have a transistor level circuit diagram of a clock buffer.By taking it as base , i have to design layout and characterize the libraray for that buffer.
And then i have to compare the results of this buffer with the results of the normal buffer after designing it as project.