ecasha
Junior Member level 2
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 module coding(clok,data,coded_out,out,rst); input [4:0] data; input clok, rst; output [1:0] coded_out; output [1:0] out; genvar i; for(i=0;i<=4;i=i+1) begin sipo str1 (.din(data[i]),.clk(clok),.dout(out),.reset(rst)); convol_enco u3 (.coded(coded_out),.in(data[i]),.p_out(out)); end endmodule
what is the problem with above code? how do i rectify it?
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