[moved]vhdl or verilog code to call a function within loop

[ecasha]

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Code Verilog - [expand]
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module coding(clok,data,coded_out,out,rst);       
input [4:0] data;    
input clok, rst;    
output [1:0] coded_out;     
output [1:0] out;    
genvar i;    
for(i=0;i<=4;i=i+1) begin   
   sipo str1 (.din(data[i]),.clk(clok),.dout(out),.reset(rst));    
    convol_enco u3 (.coded(coded_out),.in(data[i]),.p_out(out));   
    end   
endmodule

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what is the problem with above code? how do i rectify it?

 

[dpaul]

1. Post is in the wrong sub-forum, should be in ASIC or FPGA section.

2. What is it you want to do? You code shows two module instantiations (for sipo and convl_enco) inside a for loop.
Check this out for an explanation: https://stackoverflow.com/questions/25924485/using-a-generate-with-for-loop-in-verilog

 

[ads-ee]

How do you expect this to work when the loop is unrolled and all the outputs of the five (0-4) instances of u3 are all shorted together?

I think you are probably misinterpreting the code and think the loop is done sequentially in time and that you get 5 outputs one after another.