Apr 8, 2012 #1 R raghava216 Junior Member level 3 Joined Mar 10, 2011 Messages 27 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,646 I want to know how to define user defined data type in verilog? I want to define a two-dimensional array with a name say 'memory' and I want to declare a new variable of type 'memory' and assign values to it... How to do this? Plz. help
I want to know how to define user defined data type in verilog? I want to define a two-dimensional array with a name say 'memory' and I want to declare a new variable of type 'memory' and assign values to it... How to do this? Plz. help
Apr 8, 2012 #2 D dave_59 Advanced Member level 3 Joined Dec 15, 2011 Messages 841 Helped 366 Reputation 736 Reaction score 360 Trophy points 1,353 Location Fremont, CA, USA Activity points 7,390 SystemVerilog has user-defined data types, Verilog does not. In Verilog, you have to repeat the data type every time you use it; reg [width-1:] memory1 [0:dimension1-1][0:dimension2-1]; reg [width-1:] memory2 [0:dimension1-1][0:dimension2-1]; In SystemVerilog, you use a typedef typedef logic [width-1:0] memory2d_t [dimension1][dimension2]; memory_t memory1; memory_t memory2;
SystemVerilog has user-defined data types, Verilog does not. In Verilog, you have to repeat the data type every time you use it; reg [width-1:] memory1 [0:dimension1-1][0:dimension2-1]; reg [width-1:] memory2 [0:dimension1-1][0:dimension2-1]; In SystemVerilog, you use a typedef typedef logic [width-1:0] memory2d_t [dimension1][dimension2]; memory_t memory1; memory_t memory2;