[Moved] user defined data types in verilog

[raghava216]

I want to know how to define user defined data type in verilog?

I want to define a two-dimensional array with a name say 'memory' and I want to declare a new variable of type 'memory' and assign values to it...

How to do this?

Plz. help

 

[dave_59]

SystemVerilog has user-defined data types, Verilog does not.

In Verilog, you have to repeat the data type every time you use it;

reg [width-1:] memory1 [0:dimension1-1][0:dimension2-1];
reg [width-1:] memory2 [0:dimension1-1][0:dimension2-1];

In SystemVerilog, you use a typedef

typedef logic [width-1:0] memory2d_t [dimension1][dimension2];

memory_t memory1;
memory_t memory2;