sun_ray
Advanced Member level 3
Will the uncertainty be set at maximum or minimum for setup analysis during synthesis? Will the uncertainty be set at maximum or minimum for hold analysis during synthesis?
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Will the uncertainty be set at maximum or minimum for setup analysis during synthesis? Will the uncertainty be set at maximum or minimum for hold analysis during synthesis?
Read the instructions, then ask a less foggy question. On the way, learn the difference between synthesis and timing analysis.
Kevin
Till now there is no correct reply to the queries that was posted in post no 1. Can anybody answer this?
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Can you please explain more on where is the wrong you found? The question was how whether to setup the uncertainty at max or min corner and also what to do for hold. At synthesis level tool will do timing analysis including this uncertainty value.
I've never heard of synthesis using anything but wireload models for timing driven synthesis and I've never heard of a wireload model that has clock uncertainty in the model. The best synthesis timing can do is estimate the delays. A placed and routed design is required to analyze it further.
But I've been out of the ASIC flow for nearly a decade so who knows how much the tools have advanced.
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And K-J was correct in saying you should ask a less foggy question. You're question doesn't even make sense as min/max timing doesn't apply to synthesis.
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Also how can you say that there are no correct replies to the queries in post #1
You don't even know the answer, hence you asked the question. If you are such an expert and can determine correct answers then start answering other peoples questions and increasing your Helped ratio so you are at least above a 0.05 see this.
I did answer your question with a relevant answer. I told you to read the instructions. Did you? Now you're saying you want somebody who works in synthesis in ASIC flow to answer the question. Apparently you're oblivious to the fact that you posted this to the forum titled "Forum: PLD, SPLD, GAL, CPLD, FPGA Design".Let somebody who works in synthesis in ASIC flow answer the question with relevant answers to the query.
I read in the Synopsys Timing Constraint User Guide, which applies both to FPGA and ASIC design, that uncertainty will be used for ASIC synthesis if you enable a "Clock Tree Synthesis" feature. So lets assume your tools have the option to consider clock uncertainty in timing driven synthesis.
But what should be the meaning of a "maximum or minimum" uncertainty number? Uncertainty is the upper bound of clock skew, if it's put into timing calculation, the available slack will be reduced by this number, it's always making timing worse.
I did answer your question with a relevant answer. I told you to read the instructions. Did you? Now you're saying you want somebody who works in synthesis in ASIC flow to answer the question. Apparently you're oblivious to the fact that you posted this to the forum titled "Forum: PLD, SPLD, GAL, CPLD, FPGA Design".
Kevin
The tool will decrease the clock period for uncertainty number for setup analysis, and increase the period for hold analysis.
Or, you may set different values for setup and hold (usually the value for hold is bigger than for setup).