[moved] uncertainty setting at synthesis for setup and hold analysis

[sun_ray]

Will the uncertainty be set at maximum or minimum for setup analysis during synthesis? Will the uncertainty be set at maximum or minimum for hold analysis during synthesis?

 

[K-J]

Re: uncertainty setting at synthesis for setup and hold analysis

Will the uncertainty be set at maximum or minimum for setup analysis during synthesis? Will the uncertainty be set at maximum or minimum for hold analysis during synthesis?

Read the instructions, then ask a less foggy question. On the way, learn the difference between synthesis and timing analysis.

Kevin

 

[ads-ee]

Re: uncertainty setting at synthesis for setup and hold analysis

It's kind of a problem trying to use uncertainty when synthesis only has wireload models to define the delay due to the routing. The routing of everything including the clock tree is already "uncertain".

sun_ray, did you by chance switch careers from some non-technical area into engineering (without getting an engineering degree)? Based solely on your numerous posts, you seem to have difficulty in almost every aspect of engineering related work, e.g. reading/understanding datasheets, tools, design methodologies, etc.

I sincerely hope your engineering career plans aren't to be like Godzilla tromping through Tokyo leaving devastated companies in your wake.

 

[sun_ray]

Re: uncertainty setting at synthesis for setup and hold analysis

Till now there is no correct reply to the queries that was posted in post no 1. Can anybody answer this?

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Read the instructions, then ask a less foggy question. On the way, learn the difference between synthesis and timing analysis.

Kevin

Can you please explain more on where is the wrong you found? The question was how whether to setup the uncertainty at max or min corner and also what to do for hold. At synthesis level tool will do timing analysis including this uncertainty value.

 

[ads-ee]

Re: uncertainty setting at synthesis for setup and hold analysis

Till now there is no correct reply to the queries that was posted in post no 1. Can anybody answer this?

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Can you please explain more on where is the wrong you found? The question was how whether to setup the uncertainty at max or min corner and also what to do for hold. At synthesis level tool will do timing analysis including this uncertainty value.

I've never heard of synthesis using anything but wireload models for timing driven synthesis and I've never heard of a wireload model that has clock uncertainty in the model. The best synthesis timing can do is estimate the delays. A placed and routed design is required to analyze it further.

But I've been out of the ASIC flow for nearly a decade so who knows how much the tools have advanced.

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And K-J was correct in saying you should ask a less foggy question. You're question doesn't even make sense as min/max timing doesn't apply to synthesis.

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Also how can you say that there are no correct replies to the queries in post #1

You don't even know the answer, hence you asked the question. If you are such an expert and can determine correct answers then start answering other peoples questions and increasing your Helped ratio so you are at least above a 0.05 see this.

 

[sun_ray]

Re: uncertainty setting at synthesis for setup and hold analysis

I've never heard of synthesis using anything but wireload models for timing driven synthesis and I've never heard of a wireload model that has clock uncertainty in the model. The best synthesis timing can do is estimate the delays. A placed and routed design is required to analyze it further.

But I've been out of the ASIC flow for nearly a decade so who knows how much the tools have advanced.

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And K-J was correct in saying you should ask a less foggy question. You're question doesn't even make sense as min/max timing doesn't apply to synthesis.

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Also how can you say that there are no correct replies to the queries in post #1

You don't even know the answer, hence you asked the question. If you are such an expert and can determine correct answers then start answering other peoples questions and increasing your Helped ratio so you are at least above a 0.05 see this.

Probably problem is with the matter that you worked with ASIC synthesis a decade ago. Hence probably you are thinking of wire load model. We do not now use wire load model for synthesis now a days when we do synthesis. We used wire load model during synthesis many years back and afterwards used advance method instead of wire load model. There are min and max timing analysis during synthesis also. If you could answer the question properly it solves the query. Probably since you worked with ASIC flow decades ago, it is resulting this kind of irrelevant answers.

Let somebody who works in synthesis in ASIC flow answer the question with relevant answers to the query.

 

[K-J]

Re: uncertainty setting at synthesis for setup and hold analysis

Let somebody who works in synthesis in ASIC flow answer the question with relevant answers to the query.

I did answer your question with a relevant answer. I told you to read the instructions. Did you? Now you're saying you want somebody who works in synthesis in ASIC flow to answer the question. Apparently you're oblivious to the fact that you posted this to the forum titled "Forum: PLD, SPLD, GAL, CPLD, FPGA Design".

Kevin

 

[FvM]

I read in the Synopsys Timing Constraint User Guide, which applies both to FPGA and ASIC design, that uncertainty will be used for ASIC synthesis if you enable a "Clock Tree Synthesis" feature. So lets assume your tools have the option to consider clock uncertainty in timing driven synthesis.

But what should be the meaning of a "maximum or minimum" uncertainty number? Uncertainty is the upper bound of clock skew, if it's put into timing calculation, the available slack will be reduced by this number, it's always making timing worse.

 

[sun_ray]

I read in the Synopsys Timing Constraint User Guide, which applies both to FPGA and ASIC design, that uncertainty will be used for ASIC synthesis if you enable a "Clock Tree Synthesis" feature. So lets assume your tools have the option to consider clock uncertainty in timing driven synthesis.

But what should be the meaning of a "maximum or minimum" uncertainty number? Uncertainty is the upper bound of clock skew, if it's put into timing calculation, the available slack will be reduced by this number, it's always making timing worse.

Even we set no maximum or minimum for uncertainty while doing synthesis of RTL for ASIC. But I was hearing of setting maximum ans minimum for even uncertainty during synthesis. So this thread was started.

Regards

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I did answer your question with a relevant answer. I told you to read the instructions. Did you? Now you're saying you want somebody who works in synthesis in ASIC flow to answer the question. Apparently you're oblivious to the fact that you posted this to the forum titled "Forum: PLD, SPLD, GAL, CPLD, FPGA Design".

Kevin

When this thread was started, the mouse click was done on ASIC Design Methodologies and Tools (Digital). Is is a matter of wonder how it got into the forum titled "Forum: PLD, SPLD, GAL, CPLD, FPGA Design".

If you really found anything on this in any instruction, please let us know where that instruction available. The instructions or materials we have that do not state anything related to this. But there may be materials or instruction discussing this and we are not still aware of such materials or instruction. We will be happy if somebody can state about such materials availability.

Regards

 

[oratie]

It better to set the biggest uncertainty for synthesis. And then lower it during placement, CTS, routing. Still need to have some uncertainty even at sign-off STA step.

You may to set only one value of uncertainty during each step of design flow. The tool will decrease the clock period for uncertainty number for setup analysis, and increase the period for hold analysis. Or, you may set different values for setup and hold (usually the value for hold is bigger than for setup).

Hope, my explanation was clear

 

[sun_ray]

The tool will decrease the clock period for uncertainty number for setup analysis, and increase the period for hold analysis.

Will the Synopsys Design Compiler or Cadence RTL Compiler automatically decrease the clock period for uncertainty number for setup analysis, and increase the period for hold analysis?

Or, you may set different values for setup and hold (usually the value for hold is bigger than for setup).

Should we set this by turning on the setup or hold option in set_clock_uncertainty command? Will there be setup/hold option for set_clock_uncertainty command?

 

[oratie]

Synopsys DC will automatically decrease the clock period for uncertainty number for setup analysis, and increase the period for hold analysis.

You can specify different values of uncertainty for setup/hold by using "set_clock_uncertainty -setup ..." or "set_clock_uncertainty -hold ...".

If you did not specify -setup or -hold options - the same uncertainty will be upplied for both setup/hold analysis (but with different sign (decrease for setup and increase for hold).