Also I'm not sure how you compiled this code in Quartus. You are comparing a 5-bit constant with a 4-bit count value, that should throw an error in synthesis. VHDL (unlike Verilog) doesn't allow shenanigans like this.
Code VHDL - [expand] |
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| signal count: STD_LOGIC_VECTOR(3 downto 0);
constant SEC6: STD_LOGIC_VECTOR(4 downto 0) := "11001" ;
if count < SEC6 then |
I also noticed you are using a clock divider output to run the traffic instance. I would avoid using clocks generated from logic (flip-flops) in the FPGA fabric as clocks. The FPGA vendors themselves recommend that designers avoid doing this. I won't go into the details of why, there are enough resources on the subject (here and elsewhere) to find out why.