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[Moved] Traffic light controller

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alikaradag

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Hi all,
Am a new member here and hope to learn a lot from this esteemed website.
I have a vhdl code that compiles fine. The only issue is am not sure about the shape of the wave form because my Web Edition Quartus doesn't allow me to do so. Can any one help me to see the waveform shape for my code please?
the code is


Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
entity traffic_light is
port (clk: in STD_LOGIC;
clr: in STD_LOGIC;
lights: out STD_LOGIC_VECTOR (5 downto 0));
end traffic_light;
architecture traffic_light of traffic_light is
type state_type is (s0, s1, s2, s3);
signal state: state_type;
signal count: STD_LOGIC_VECTOR(3 downto 0);
constant SEC6: STD_LOGIC_VECTOR(4 downto 0) := "11001" ;
constant SEC1: STD_LOGIC_VECTOR(4 downto 0) := "00100";
begin process (clk, clr)
begin
if clr = '1' then
state <= s0;
count <= X"0";
elsif clk'event and clk = '1' then
case state is
when s0 =>
if count < SEC6 then
state <= s0;
count <= count + 1;
else state <= s1;
count <= X"0";
end if ;
when s1 =>
if count < SEC1 then
state <= s1;
count <= count + 1;
else state <= s2;
count <= count + 1;
end if ;
when s2 =>
if count < SEC6 then
state <= s2;
count <= count + 1;
else state <= s3;
count <= X"0";
end if;
when s3 =>
if count < SEC1 then
state <= s3;
count <= X"0";
else
state <= s0;
count <= X"0";
end if ;
when others => state <= s0;
end case;
end if;
end process ;
C2:
process (state)
begin
case state is
when s0 => lights <= "100001";
when s1 => lights <= "010001";
when s2 => lights <= "001100";
when s3 => lights <= "001010";
when others => lights <= "100001";
end case;
end process;
end traffic_light;
library ieee;
use ieee.std_logic_1164.all;
entity traffic_light_top is
port ( clk : in STD_LOGIC;
btn : in STD_LOGIC_VECTOR(3 downto 3);
ld : out STD_LOGIC_VECTOR(7 downto 2));
end traffic_light_top;
architecture traffic_light_top_arc of traffic_light_top is
component clkdiv is
port ( mclk : in STD_LOGIC;
clr : in STD_LOGIC;
clk3 : out STD_LOGIC );
end component ;
component traffic is
port (clk: in STD_LOGIC;
clr: in STD_LOGIC;
lights: out STD_LOGIC_VECTOR(5 downto 0));
end component;
signal clr, clk3: STD_LOGIC;
begin
clr <= btn(3);
U1: clkdiv
port map
( mclk => clk, clr => clr, clk3 => clk3 );
U2: traffic
port map
( clk=>clk3, clr=>clr, lights=>ld );
end traffic_light_top_arc;

 
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sharath666

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What do you mean by shape of the waveform? Do you mean to say you cannot simulate and check this code?
 

sharath666

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Why don't you try using another simulator like modelsim?
 

ads-ee

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Why can't you use the Altera Modelsim Starter Edition? https://www.altera.com/products/software/quartus-ii/modelsim/qts-modelsim-index.html. It's free and can run simulations of 10,000 lines of code. Your code is quite a bit less than 10K lines.

- - - Updated - - -

Also I'm not sure how you compiled this code in Quartus. You are comparing a 5-bit constant with a 4-bit count value, that should throw an error in synthesis. VHDL (unlike Verilog) doesn't allow shenanigans like this.

Code VHDL - [expand]
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signal count: STD_LOGIC_VECTOR(3 downto 0);
constant SEC6: STD_LOGIC_VECTOR(4 downto 0) := "11001" ;
if count < SEC6 then



I also noticed you are using a clock divider output to run the traffic instance. I would avoid using clocks generated from logic (flip-flops) in the FPGA fabric as clocks. The FPGA vendors themselves recommend that designers avoid doing this. I won't go into the details of why, there are enough resources on the subject (here and elsewhere) to find out why.
 

alikaradag

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Why can't you use the Altera Modelsim Starter Edition? https://www.altera.com/products/softw...sim-index.html. It's free and can run simulations of 10,000 lines of code. Your code is quite a bit less than 10K lines.

Oh really!
I will try it now and let you know!

You are right in regard to the 5-bit constants, yet it was compiling fine! Anyway, I corrected the code.

Thanks

Also I'm not sure how you compiled this code in Quartus. You are comparing a 5-bit constant with a 4-bit count value, that should throw an error in synthesis. VHDL (unlike Verilog) doesn't allow shenanigans like this.

Code VHDL - [expand]
1
2
3
signal count: STD_LOGIC_VECTOR(3 downto 0);
constant SEC6: STD_LOGIC_VECTOR(4 downto 0) := "11001" ;
if count < SEC6 then



I also noticed you are using a clock divider output to run the traffic instance. I would avoid using clocks generated from logic (flip-flops) in the FPGA fabric as clocks. The FPGA vendors themselves recommend that designers avoid doing this. I won't go into the details of why, there are enough resources on the subject (here and elsewhere) to find out why.

- - - Updated - - -

It works :)
Thank you sooooooo much ads-ee
Really appreciate you and this amazing website.


Why can't you use the Altera Modelsim Starter Edition? https://www.altera.com/products/software/quartus-ii/modelsim/qts-modelsim-index.html. It's free and can run simulations of 10,000 lines of code. Your code is quite a bit less than 10K lines.
 
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TrickyDicky

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Also I'm not sure how you compiled this code in Quartus. You are comparing a 5-bit constant with a 4-bit count value, that should throw an error in synthesis. VHDL (unlike Verilog) doesn't allow shenanigans like this.

Code VHDL - [expand]
1
2
3
signal count: STD_LOGIC_VECTOR(3 downto 0);
constant SEC6: STD_LOGIC_VECTOR(4 downto 0) := "11001" ;
if count < SEC6 then



This code is fine - though you may get a warning. Comparing strings of different lengths is legal VHDL, but it will always return false.

- - - Updated - - -

This code is fine - though you may get a warning. Comparing strings of different lengths is legal VHDL, but it will always return false.

Actually in this case - its even more interesting. As std_logic_unsigned is used, it SHOULD compare the different string lengths just fine. But in this case, count is ALWAYS less than SEC6. Hence the expression is always true.
 

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