[Moved]: problems with Capacitor layout (MIMCAPS_MM)

[Vishnudas Thaniel S]

Hi all,

Can anybody tell me abut how to layout a MIMCAPS_MM capacitor in cadence Virtuoso. I want to know which all metal layers are to be used for this. Is there any labelling required. I am using UMC 180 nm process. Iam quite new to layout . I am stuck with this for quite some time . Please help.

Thank you

 

[erikl]

MIMCAPS are handled differently in various design kits. I don't know the UMC 180 nm one, so I'd suggest to search in its PDK docu for a description, and/or in its libraries for a corresponding symbol, simulation model and layout. If available, study the layout for its layer and via usage and the necessary recognition layer for the extract tool.

Usually you use standard units with a multiplier, or state its W & L dimensions (Pcell).

Most of the MIMCAPS which I know use an extra metal layer below the top-most layer, or, possibly, above the next metal layer below the top-most one, with an extra rather thin dielectric layer in between, to achieve a large cap/area ratio.

In this post you can find a MIMCAP example from a different 0.18µm design kit.