didid
Newbie level 4
Hello everyone.
I am having difficulties in post-simulation after extracting PEX data.
View attachment 193242
The picture above is my schematic for neural recording.
I extracted all the PEX data of each sub-block circuit and I made the schematic into one symbol to do post-simulation.
View attachment 193243 View attachment 193244
As you can see in those 2 pictures, the left one is simulated with PEX data of each sub-block, while the right one is for the entire symbol.
The results of the two simulations were too different.
View attachment 193245
The transient output of the LNA and the transfer function of the schematic are different.
The pink graph on the left and the green graph on the right are the results of the sub-block PEX simulation.
and the purple graph on the left and the blue graph on the right are the results of the whole symbol PEX simulation.
Do you know why this is happening?
The devices used in the schematic besides the sub-block are capacitors. In my opinion, there is a problem when extracting the PEX data of those capacitors.
How can I solve this problem? Should I make layout routing again?
I'd love to hear your opinion.
I am having difficulties in post-simulation after extracting PEX data.
View attachment 193242
The picture above is my schematic for neural recording.
I extracted all the PEX data of each sub-block circuit and I made the schematic into one symbol to do post-simulation.
View attachment 193243 View attachment 193244
As you can see in those 2 pictures, the left one is simulated with PEX data of each sub-block, while the right one is for the entire symbol.
The results of the two simulations were too different.
View attachment 193245
The transient output of the LNA and the transfer function of the schematic are different.
The pink graph on the left and the green graph on the right are the results of the sub-block PEX simulation.
and the purple graph on the left and the blue graph on the right are the results of the whole symbol PEX simulation.
Do you know why this is happening?
The devices used in the schematic besides the sub-block are capacitors. In my opinion, there is a problem when extracting the PEX data of those capacitors.
How can I solve this problem? Should I make layout routing again?
I'd love to hear your opinion.