[Moved]: Mismatch between expected and simulated patterns in scan serial

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chaitanyavarma007

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Hi,
I was performing simulation(scan_serial) in synopsys vcs for one block named rx_pd after performing pattern retargetting.
I got an error saying that Mismatch occurred
Signal name: SEL_VAUX_B
timestamp : 31290ns
instance : topmodule/submodule/core/edt_rx_pd_channel2
Simulated : x
Expected : 1
The signal is found in topmodule,but its value is x in submodule and core.
How to resolve it?
 

Read simulation log and find the violation line
 

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